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i2c_master
- This details an I2C master component for single master buses, written in VHDL for use in CPLDs and FPGAs. The component reads and writes to user logic over a parallel interface. It was designed using Quartus II, version 11.1. -This details an I2C mas
i2c_master_bit_ctrl
- I2C控制总线主机,按照字节写设计的verilog代码,由于选项中没有verilog这项,因此选择VHDL-I2C control bus master, according to the byte write verilog code design, because the option is not verilog this, so choose VHDL