搜索资源列表
SDR_SDRAM_IP
- SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
CIC32
- cic滤波器，没有用ip核，用vhdl语言写的32倍抽取，4阶，经过验证-cic filter, did not use ip core, the language used to write 32 times vhdl extract, 4 bands, proven
ahb_mas.tar
- its shows the ip of amba ahb master in vhdl
i2c_master_slave_core_latest.tar
- IIC IP核，可以直接集成在SOPC中的(⊙o⊙)哦-基于Quartus II 可直接集成到SOPC，自定义II C IP核
IP-code(8051-cpu-jtag-vga_lcd-i2c)
- ip核源码，包含8051,cpu,jtag,vga_lcd,i2c，使用vhdl语言编写，-ip nuclear source, including 8051, cpu, jtag, vga_lcd, i2c, using vhdl language,
fft256
- quartus ii 中利用ip核生成fft模块，实现256点fft功能-quartus ii the use of nuclear generation fft ip module to achieve the 256 point fft function
AES-sopc--ip
- 在FPGA上实现了AES，并写了基于AVALON总线的接口，主要使用是VHdL实现，并在SOPC系统上定制了IP核。-FPGA to realize the AES, and write the AVALON based on the bus interface, the main use is VHdL implementation, and the SOPC system in custom made IP core.
IP-coreincluding-VHDL-and-Verilog
- 芯片设计必须解剖的IP核（包含VHDL和Verilog代码）-The IP core chip design must anatomy (including VHDL and Verilog code)
OneWireMaster
- 美信onewire总线IP core,带验证激励-MAXIM DS1WM Synthesizable 1-Wire Bus Master IP core.
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
sunset-vhdl
- 小精灵自爆：采用64*4位ip核并随机赋值作为地图信息，小精灵具有一定血量，可以在地图上面根据周围敌人（赋值为1)数量和自己血量选择是否进行自爆。-Elf blew: 64* 4 ip nuclear and random assignment as the map information, the elves have a certain amount of blood, the map above surrounding enemies (a value of 1) the number a
time
- FPGA做的电子钟，通过定时器实现。用vhdl做的led ip核，软件实现控制显示-FPGA do electronic bell, by timer implementation. Led ip vhdl do with nuclear, software control display
cheap_ethernet_latest.tar
- 用fpga实现的以太网ip协议，能实现1000m的速度，实现简单！-ip vhdl
IP
- USB+UART+I2C+VGA+ARM7+MC8051 altera IP核-USB+UART+I2C+VGA+ARM7+MC8051 Verrlog VHDL
mc8051_design
- 使用VHDL语言，实现C8051 IP Core(Use VHDL, Realize C8051 IP Core)
smg_IP
- 在DE 2开发板上，编写vhdl语言，建立8段数码管IP核，在nios ii中编写C语言程序，实现8段数码管数码有规律显示。(In the DE 2 development board, the preparation of VHDL language, the establishment of 8 sections of digital tube IP kernel, in Nios II written in C language program, to achieve the 8 sect
ethernet 10-100 monitoring
- this is using mac IP core for ethernet connection in ISE xilinx for ethernet 10/100
MY 80c51 IP
- verilog和vhdl混写的工程 内含mc8051软核及最小系统 经测试已调通(Verilog and VHDL mixed with the project, including the mc8051 soft core and the smallest system, the test has been transferred)
10419729vhdl对数
- 进行对数运算的IP核，可以计算以2，10，e为底的对数，最高可输入24bit宽度的数据。 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。(The IP kernel that performs logarithmic operations can compute data at the base of 2, 10, and E, with the highest input 24bit width. Written in AHDL language, can