搜索资源列表
NAND_IP
- Nand flash VHDL code and Nand flash verilog code
lcd_drv
- IP core for LCD controller of Xilinx FPGA
100M_mac
- 100M MAC IP opencores
sdram_ver_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is based Xilinx FPGA Playform.
UARTipcore
- 这是一个关于UART的IP核，用VHDL写的。经过本人的鉴证，非常实用并且写的非常好。-This is one of the IP core on the UART, using VHDL written. After my verification, very practical and very well written.
pci_32tlite_oc
- 嵌入式 pci总线IP core的rtl源代码，用Verilog实现-Embedded pci bus IP core of the rtl source code, Verilog realization of
components
- quartus的几个IP核（PWM,RAM,I2C）-quartus several IP core (PWM, RAM, I2C)
qam_64
- 64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核-64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS
W5100_driver_source_20070309
- Wiznet TCP IP Stack for embedded microcontrollers.
FFT
- IP核！！高速傅立叶变换的VHDL源代码 可以综合-IP core! ! High-speed Fourier transform of the VHDL source code can be integrated!!
IPcore
- 非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
364652261
- FIFO一个用IP核调用的控制程序，里面有调用的IP核和FIFO读写控制-FIFO with an IP core call control procedures, which are called IP core and FIFO read and write control
core_arm
- 从opencore找都的ARM的IP CORE。有详细说明。-From opencore to find all of the ARM' s IP CORE. Is described in detail.
I2CSLAVE
- 已经验证过的I2C，slave的IP，core，从一开源网站下载的，代码写的非常好，节省了FPGA的资源，比起以往的slave的CORE，这个CORE减少了寄存器的使用。-Has been verified I2C, slave of the IP, core, from an open source website, the code is written in a very good save FPGA resources than the previous slave of CORE, t
uart16550_latest[1].tar
- 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character lengt
ac97_latest.tar
- simple AC97 Controller IP core. It supports one AC97 codec, with 6 output and 3 input channels. This AC97 Controller s fully AC97 Revision 2.2 compliant. it only supports AC97 Audio Codecs.
C8051_mega_core.tar
- 8051单片机软核，测试代码和仿真环境，可直接上fpga使用，是一个成熟的ip核。经本人仿真以及在fpga上测试，完全正常。-8051 soft ip core, testbench, simulation environment
d
- IP核应用，详细的介绍了关于FPGA中IP核的应用-IP core application, a detailed presentation on the application of FPGA in the IP core ,,,,,,
8051code
- VHDL源码 8051+IP内核 在xilinx环境仿真运行 不带接口的逻辑部分代码-VHDL source code 8051+ IP cores in the xilinx environment simulation to run without a logical part of the code interface
i2c
- i2c master controller, free ip