搜索资源列表
frequency_meter_VHDL
- 一个用VHDL完成的8位数显的16进制的频率计-a VHDL completed 8 of 16 significant median band of frequency meter
fifo_01
- 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8 -- 8-bit Identity Comparator -- uses 1993 std VHDL --
FPGA-drivenLEDdisplay
- FPGA驱动LED显示:运用硬件描述语言（如VHDL）设计一个显示译码驱动器，即将要显示的字符译成8段码。由于FPGA有相当多的引脚端资源，如果显示的位数N较少，可以直接使用静态显示方式，即将每一个数码管都分别连接到不同的8个引脚线上，共需要8×N条引脚线控制.-FPGA-driven LED display: the use of hardware descr iption languages (such as VHDL) design a display decoder driver, ab
median_filter
- 实现图像中值滤波的VerilogHDL源代码-Median_filter VerilogHDL Code
MovingAverageFilter
- This zip file contains the moving average filter code written in verilog HDL
1002
- median filter algorithm help
med01-165
- median filter details
eytruytf.u
- implementation of median filter
MULTIPLIER
- 基于VHDL硬件描述语言设计的乘法器，位数可以修改-VHDL hardware descr iption language based on the design of the multiplier, the median can be modified
mid-filter
- mid-filter 中值滤波算法的原理及核心代码 word版-mid-filter median filter and the core principles of the code word version
mid01
- 中值滤波的VHDL语言，包括所有的工程，工程中包含所有的模块程序-Median filtering VHDL language, including all engineering, engineering program contains all the modules
filter
- 用vhdl硬件描述语言写的中值滤波器，主要对尖峰脉冲进行消除。在fpga上实现。-Vhdl hardware descr iption language used to write the median filter, mainly to eliminate spikes. Implemented on the fpga.
a-VHDL-completed-8-of-16-significant-median-band-
- a VHDL completed 8 of 16 significant median band of frequency meter
zzlB
- QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。-the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing.
mul
- VHDL实现通用乘法器，位数可以自定义，通过移位相加实现-VHDL generic multiplier, the median can customize the sum achieved by shifting
Vmidd-filtterH
- 用vhdl语言实现的中中值滤波，硬件需要DE2板 -Use the vhdl language in median filtering, the hardware needs DE2 board
Median-Module
- Median Module VHDL code
med_filter
- 基于图像处理的中值滤波VHDL源码,能够实现对图像的滤波-Based on the median filter VHDL source image processing, image filtering can be achieved
Multiplier
- 我是2014级复旦的研究生。这是用VHDL语言设计的任意的M乘以N位的乘法器。设计中，被除数和乘数的位数是通过参数来设置的，可由你来修改。我已写好了testbench。可放心使用。-I am a 2014 graduate of Fudan University. This is an arbitrary M VHDL language designed by N-bit multiplier. Design, the dividend and the median multiplier is
filters_FPGA2
- this is vhdl code of median filter