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16位的移位寄存器，加上testbench,可以在modelsim里面运行~-16 of the shift register and testbench, modelsim the inside running ~
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modelsim工程，用verilog实现的HDB3编码，以及测试程序testbench-modelsim works with verilog realized HDB3 coding, and testing procedures testbench
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riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
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此代码实现不同图像颜色制式之间的相互转换，如XYZ<->RGB, 不同标准的RGB<->RGB 以及RGB<->YCbCr之间的转换，包内含有matlab仿真代码m文件、VHDL代码.v文件以及modelsim仿真的testbench文件，相信对大家有一定的帮助
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altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim
验证，文件中包含TESTBENCH ，直接可用
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脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench
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本算法基于leon2协处理器接口标准，内含testbench，在modelsim中仿真通过，在ise9.2中综合及后仿真通过。,The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
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HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is li
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sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl
\doc DDR SDRAM reference design documentation
\model Contains the vhdl SDRAM model
\route Contains the Quartus 2000.05 project files a routed controller design
\simulation
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Simple LZW image compression implemented on Spartan-3e starter kit using Xilinx9.2 and Modelsim for testbench simulation.
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And gate testbench, testbench to simulate and run in modelsim
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vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
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I2C总线接口的Verilog源码文件和modelsimd的测试文件-Verilog source code of I2C bus interface and testbench code of modelsim.
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包括一个基于Quartusii的加法器工程，以及基于ModelSim的前仿真、综合后功能仿真和布局布线后时序仿真的完整例程及testbench文件，吐血推荐，非常有用！-Includes an adder based Quartusii works, and the first based on ModelSim simulation, synthesis functional simulation and post layout timing simulation after complete
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4位全加法器的modelsim工程带testbench-Four full-adder modelsim project with testbench
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32位bit输入的CRC32校验，verilog的代码，以及modelsim的testbench代码-The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench
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verilog hdl 开发的频率计，运行环境 DE2-115开发板，内有modelsim仿真用的testbench。RTL级代码-verilog hdl developed frequency meter, operating environment, the DE2-115 development board, modelsim simulation of the testbench. RTL-level code
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此為採用ALTERA所做的DDR 控制器(verilog)-
File/Directory Descr iption
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\doc DDR SDRAM reference design documentation
\model Contains the verilog SDRAM model
\route
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SPI FLASH官方仿真模型方便modelsim testbench调试仿真(Official simulation model facilitates debugging and simulation)
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