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loongson
- 龙芯2E处理器用户手册 中国科学院计算技术研究所 意法半导体公司 2006年 9 月 龙芯2E处理器是一款实现64位MIPS III 指令集的通用RISC处理器。龙芯2E的指 令流水线每个时钟周期取四条指令进行译码，并且动态地发射到五个全流水的功能部件 中。虽然指令在保证依赖关系的前提下进行乱序执行，但是指令的提交还是按照程序原 来的顺序，以保证精确中断和访存顺序执行。 -Godson 2E processor user manual CAS Institute of Comp
Godson1
- 龙芯一号的数据手册！ 通用32 位微处理器，支持MIPS-III 指令 主频为200~266MHZ 基于操作队列复用的高效7 级标量流水线 高效的64 位浮点流水单元 浮点性能220 MFLOP @250MHz 内置MMU、TLB 实现从程序虚拟地址到CPU物理地址的转换-Godson manual data on the 1st! Definitive 32 microprocessor, support MIPS-III Directive megabyte of 2
dlx
- mips pipeline 模以程序，mfc实现的，功能就不用说了把，大家都知道的-MIPS pipeline to die procedures mfc achieve, and functions not have had to put, we all know the
MipsIt
- 可以自由开发的MIPS仿真器模型(.exe),指令执行动画显示.通过修改graphics和对应的元件和互联文件(.dit)可以自己画流水线,其中.dit文件使用简单的硬件描述语言编写.而mipsit是对应的软件开发环境,为自己设计的流水线编程.学习体系结构的好东西-This is a system consisting of a software development environment and a highly flexible microarchitecture simulator
Simulator
- 基于VC++的MIPS五级整数流水线模拟系统，附有设计文档与源代码。-VC++ for MIPS based on five integer pipeline simulation system, with design documents and source code.
instruction_decode_v
- MIPS 5 stage pipeline, this file is for instruction decode. you can use it to place in pipline. this has been used in a study lab.
Simulators
- 基于VC++的MIPS五级整数流水线模拟系统，附有设计文档与源代码-VC++ for MIPS based on five integer pipeline simulation system, with design documents and source code
spim-8.0
- 一个模拟MIPS结构cpu的程序，完成cpu的基本功能，用于模拟5级流水cpu-Structure of a simulated MIPS cpu' s program, complete the basic functions of the cpu, used to simulate the 5-stage pipeline cpu,
project
- s-stage MIPS pipeline with forwarding unit implemented in quartus ||
MIPS_Pipelined_CPU
- MIPS Pipelined CPU written on VHDL with commands, 5 stage pipeline
Scordbord-Mips-Pipeline
- this a scorbording mips hazards and multiple functional units with different latency -this is a scorbording mips hazards and multiple functional units with different latency
7065381-Ky-Thuat-Pipeline
- the file help pipepline MIPS 5 and 8. english.pipepline pipep line pipepline -the file help pipepline MIPS 5 and 8. english.pipepline pipepline pipepline pipepline
vhdl-pipeline-mips_latest
- pip-lined MIPS in vhdl
simple-pipeLine-CPU
- 简单的流水线CPU实现，基于MIPS指令集。-Simple pipelined CPU implementation, based on the MIPS instruction set.
MIPS Pipeline
- A program to simluate the MIPS pipeline
lab28
- 采用5级流水线MIPS微处理器设计，实现32位流水线的算数、逻辑、以为等指令-pipeline MIPS
PIPELINE
- （包含详细说明文档和简单汇编转机器码翻译器）五级流水线实现MIPS指令集（30条）含异常处理。结构采用多分支预测结构（基于历史的动态分支预测）-(Contains detailed documentation and compilation turn simple machine code translator) five pipelined MIPS instruction set (30) with exception handling. Structure using multi-bran
pipelined-mips-cpu-master
- misp 5 stage pipeline
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
mips
- 基于mips架构的五级流水线硬件实现。使用verilog-Based on the five-stage pipeline hardware architecture mips