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68_alarm_controller
- vhdl源程序，在quartus环境下测试，仿真。已经过测试。-VHDL source, the Quartus environment testing, simulation. Has been tested.
78_alu_input
- vhdl源程序，在quartus环境下测试，仿真。已经过测试。-VHDL source, the Quartus environment testing, simulation. Has been tested.
key_scan1
- 用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功-achieved using Verilog 4 x 4 keyboard procedures, the Quartus II compiler on the adoption and successful
signalgenerater
- 一个简单的多种信号的发生器 包括正玄，锯齿，阶梯等，使用时用quartus 4.0以上版本打开-a simple multiple signal generator including Shogen, sawtooth, the ladder, when used with the above version 4.0 Quartus open
mycounter
- quartus 中文wj-Quartus Chinese wj
VHDL_processor
- 利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.-use VHDL descr iption of a simple microprocessor, can modify the source codes to adjust instruction set, Quartus II can be directly compiled and running.
VHDL-Clock
- 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
ref-ualaw
- A率/u率 压缩与解压缩的IP核，。 # 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。-A rate / u rate compression and decompression of the IP core,. By AHDL # languages, and the Quartus II MaxplusII use, the source code encryption.
硬件求解平方根
- 硬件求解平方根源代码加密 (硬件求解平方根的，将license添加到原有的MaxplusII或QuartusII的license中就可以直接使用，但源代码加密。altera提供 )-solving square root of the hardware encryption code (square root of the hardware solution will be added to the original license MaxplusII or Quartus II of the
quartus_Chinese_Introduction
- quartus 软件应用中文教程，包含一些高级的用法等。-quartus Chinese Directory software applications, including some senior usage, and so on.
multiplex
- 复接程序,用quartus运行的,可以把很多个信号复接在一起,是程序的一部分!-Multiplexing procedures used quartus operations, can put a lot of signal multiplexing together, is part of that process.
intro_to_quartus2_v6.0_chinese
- quartus II 6.0 中文使用手册 intro_to_quartus2_chinese-Chinese quartus II 6.0 manual intro_to_quartus2_ english
seq_gen_576
- 高清电视HDTV信号发生器，576P逐行，VHDL语言，ALTERA的Quartus II开发平台-HDTV HDTV signal generator, 576P progressive, VHDL, Altera's Quartus II development platform
counter60
- 这是我们做的一个作业 摸60计数器，用Quartus ii 做的 ，内容齐全 不可不看。-This is the one we do feel 60 counter operation with Quartus ii do. complete contents can not see.
videofram
- 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
altera_lcd_controller
- quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
VHDL_Memory_Library_Code
- 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
CrackQII60
- quartus6.0+nios2 6.0的License,将hostid改为你自己的网卡号即可使用quartus和nios6.0的全部功能-quartus6.0 nios2 6.0 License, hostid to read your own card can be used quartus, and the full functionality of nios6.0
Crack_QII60_b178
- Quartus II 6.0完全Crack文件-Quartus II 6.0 document completely Crack
multi8x8
- 节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证-resource conservation-8 * 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test