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jiaotongdeng
- 本代码是基于DE2开发板做的实验,使用的编程软件是Quartus II 9.0。它实现的功能是十字路口的交通灯控制,并且在红灯转为绿灯时有1S延迟。-This code is based DE2 development board to do the experiment, the Quartus II 9.0 programming software. It implements the functionality is the crossroads of traffic light cont
uart_lcd
- 串口控制LCD1602显示的源码 开发软件:Quartus II 9.0 (32-Bit) 硬件:EP1C12-Serial control the the LCD1602 display of source development software: Quartus II 9.0 (32-Bit) Hardware: EP1C12
sram_uart_tx
- 将SRAM中的数据通过串口发送到电脑上。 软件:Quartus II 9.0 (32-Bit) 硬件:EP1C12-SRAM data is sent to the computer through the serial port. Software: Quartus II 9.0 (32-Bit) Hardware: EP1C12
Counter10
- 在quartus 9.1软件上用verilog语言编写的10进制计数器程序-The Verilog language quartus 9.1 software 10 binary counter program
2dpsk4
- vhdl实现2dpsk,软件是Quartus II 9.0 (32-Bit)-2dpsk VHDL
0-8anjian
- 用FPGA实现的按键程序,9个按键显示数字0~8,已在quartus里面成功编译并用FPGA板验证过-failed to translate
EP2C8-2010_FPGA
- EP2C208C8 FPGA开发源代码(芯蓝C8板) turn_on_led 点亮LED sw_led 拨动开关控制LED rider_led 跑马灯 water_led 流水灯 key_led_without_debounce 轻触开关控制LED,无按键去抖 key_led_with_debounce 轻触开关控制LED,有按键去抖 seg7x8_dynamic_disp 七段数码管动态显示 matrixKeyb
asynchronous-fifo
- 同步fifo的调用程序,调用Quartus II 9.0 (32-Bit)中的fifo模块-Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module
Phone-Call-Meters-by-Quartus9.2
- 本次设计主要基于FPGA器件完成了一个IC电话计费器的设计,其能够显示用户IC的卡值余额,并能够根据用户当前的话务种类和通话时间进行扣费,并将用户的实时余额和通话时间通过4位LED七段显示器显示出来。整个设计过程采用自顶向下的分块设计方法,即将整个电话计费系统分为电话计费、计时模块和显示模块两大模块,其各模块的实现是基于QuartusⅡ9.2平台使用DE0硬件描述语言编程实现的。-This design is mainly based FPGA devices completed a telep
9-multiple-9
- quartus II 下 VHDL实现 九九乘法表-Quartus II VHDL 9 multiple 9
8051_test
- 在FPGA上,可用的8051核。用Quartus II 9.0调试通过。-On the FPGA, available 8051. With Quartus II 9.0 debugging.
vhdlquartusfft16
- fft16 点, quartus2 9.0 用vhdl编写各个模块,然后用电路图形式连起来 如有问题 plklklklkl@sina.com 里边还有 报告-ffft 16 quartus
2freq_uart_se
- 高精度串口频率计VHDL源码,开发环境为Quartus II 9.0,频率范围为0-1MHz-Precision frequency meter serial VHDL source code, development environment for Quartus II 9.0, the frequency range of 0-1MHz
clock_end
- 基于Quartus II 9.0 的电子时钟,用VHDL语言编写,显示时钟,星期等,可以调整。-Quartus II 9.0-based electronic clock, using VHDL language, display clock, week, etc., can be adjusted.
LED
- QuartusII 9下的LED灯示例,很简单的例子,可以直接运行-The sample of LED of quartus II 9.0 with the language of Verilog
DE2_i2sound
- Altera DE2开发板例程源码,原版的为基于quartus II 7.2开发的,在9.0以上的版本上编译通不过,本源码为基于quartus II 9.0以上版本-Source code of Altera DE2 development board
DE2_NET
- DE2开发板例程源码,FPGA:EP2C35F256C6,代码基于quartus II 9.0以上的版本(随板光盘的为7.2的版本,在9.0以上的版本上编译通不过会报错)。该代码主要功能为FPGA对以太网通信,与PC机通信-In this demonstration, we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 board. We use the
DE2_NIOS_HOST_MOUSE_VGA
- 本代码为DE2开发板例程源码(EP2C35F672C6),项目基于quartus II 9.0(随板光盘为7.2版本以下,在9.0版以上编译会报错)。本项目实现一个USB画笔功能,通过FPGA控制USB口,USB口接上鼠标,通过XGA口外界显示设备,实现显示设备对鼠标移动轨迹的显示。-In this demonstration, we implement a Paintbrush application by using a USB mouse as the input device.This
DE2_TV
- 本代码为Altera DE2开发板例程源码,(FPGA:EP2C35F672C6)quartus II 9.0以上可以编译(随板源码为7.2以下版本,在9.0以上版本编译会报错)。本代码实现一个音视频播放器TV_BOX。-This demonstration plays video and audio input a DVD player using the VGA output and audio CODEC on the DE2 board. There are two major bl
lock
- 基于VHDL的智能密码锁程序,能用EMP1270T144C5单片机下载,能够输入4—6位十进制密码,有重置密码、报警、点阵显示、数码管显示功能。quartus II 9.0编译成功。压缩包里有word文件的源码,打不开工程可以看看。代码较多但语句都很简单,有比较详细的注释。-VHDL-based smart lock program, can download EMP1270T144C5 microcontroller can enter 4-6 decimal code, there are