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sinput
- 在matalab上建立sin函数完成一个数据库，放入quartus中建立ip核，对其进行仿真-Sin in matalab function to complete the establishment of a database to create quartus Add ip nuclear, its simulation
Avalon_VGA
- vga显示彩色图像ip，alter开发板-vga display color image,vhdl,quartus
oc_i2c_master_v92
- I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
oc_i2c_master_bit_ctrl_v92
- I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
stratixIII_3sl150_dev_TSE_SGMII_v1
- 该程序实现altera开发板 stratix III 3S150通过以太网与pc之间通信。 使用Quartus II和Nios II 设计。 因为altera官方没有这块板子的正确网卡与pc通信的程序，-Overall This example works at 1000M/100M/10M Base SGMII mode on SIII 3S150 Kit. Designed by Quartus II/IP Cores/Nios II EDS v8.0 This is not
i2c
- I2C IP CORE Verilog quartus-I2C IP CORE Verilog quartusii
I2C
- 本文件是在quartus II环境下编译的，功能为I2c控制模块。可作为IP核使用！-This document is compiled in quartus II environment, the function I2c control module. Can be used as IP core to use!
BPSK
- 在quartus ii下完成的用VHDL语言编写的数字式调频BPSK的调制，其中DDS和成型滤波使用ip核完成-Accomplished in quartus ii the use of VHDL language digital FM BPSK modulation, which use the ip filter DDS and forming complete nuclear
sram_lcm
- 该代码是基于NIOSii软件在QUARTUS上上自制IP核并在DE2开发板实现图片的显示。-The code is based on NIOSii software QUARTUS made on the IP core and on the DE2 board to achieve the picture display.
quartus_IPcore
- 这15个Quartus的ip核里面有AVR，I2C，sdram，arm，usb，PCI等ipcoure，相信用过ipcore的人都知道这个的重要性，尤其是在NIOS嵌入硬件以提高速度的时候，这些事非常有用的。毕竟这些事人家封装起来的，肯定比自己去编好吧，献给用Quartus的好盆友，希望对你们有用。-free ipcoure
Picture_Downloader
- Picture downloader IP using Quartus II via JTAG
MIF_file_of_Sine_Wave_Generator
- 在Quartus的DDS设计中，通常会用到mif或者hex文件存储函数值，被ROM的IP模块调用。本程序是在Matlab环境下，根据所需数据位数和长度自定义mif文件。-Quartus DDS design, usually used in the mif or hex file storage function value, call the ROM of IP modules. This program is in the Matlab environment, according to t
NCO
- 利用Quartus中的IP核进行NCO的设计源文件-IP cores in Quartus NCO design source files
DDS
- Quartus环境下，使用VHDL语言和IP核进行的通用DDS设计。-Quartus environment, general DDS design using VHDL and IP cores.
VIP_scaler
- FPGA处理图像缩放的工程模块，是在Quartus II里面调用VIP中的Scaler IP核做的-FPGA processing project module, image scaling is done in the Quartus II which calls VIP Scaler IP Core
022-FIFO_PRO
- verilog写的控制quartus自带fifo ip核的程序-verilog to write the control quartus own fifo ip nuclear program
qcomponentsu
- quartus的几个IP核（PWWM,RAM,I2C） -quartus several IP cores (PWWM, RAM, I2C)
reg8_hdl
- 8段数码管驱动程序，可直接在quartus II上添加到sopc中，生成IP核。-8 digital tube driver, can be directly added quartus II to sopc in the generated IP core.
AM
- Quarus环境下用VHDL语言和IP核实现AM调制-Realization of AM with VHDL and IP core under Quartus environment
tongbu
- FFT实现信号的检测与同步，使用FFT做相关运算，大大缩短了了同步的复杂度和时间，这里是主代码，其他模块QUARTUS中自带有IP核，直接调用就是了-FFT signal detection and synchronization, do the relevant calculations using FFT, greatly reducing the complexity and time synchronization, here is the main code IP core comes