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ref-ualaw
- A率/u率 压缩与解压缩的IP核,。 # 由AHDL语言写成,可在MaxplusII和QuartusII中使用,源代码加密。-A rate / u rate compression and decompression of the IP core,. By AHDL # languages, and the Quartus II MaxplusII use, the source code encryption.
altera_lcd_controller
- quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
VHDL_Memory_Library_Code
- 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
fft_IPcore
- 这是一个fft的IP核,安装要求为quartus6.0以上。解压安装后可在quartus里例化使用,元件主要为cyclone和stratix,最大支持1024点的转换。
sd_audio_aic23
- SD卡和AIC23数字音频输出实验, FreeDev Audio Dsp Board采用了TI公司的TVL320AIC23 1、控制接口使用I2C,Quartus中将CS置低(器件地址0011010)。 2、数字音频接口使用了组件FreeDev_aic23,有三种测试和应用 模式,中断结合DMA方式能在NIOS II中采集和发送数据。中断信号 产生于模块中FIFO缓冲区的半满信号,读取数据端口自动清除中断 请求信号。 3、I2C IP 和FreeDev_aic23 IP分别在Qu
fftsoft
- 应用altera的最新fft核做的使用范例,fft核遵循avalon总线。对于想使用altera的IP core的朋友有帮助-Application of nuclear altera do the latest example of the use fft, fft nuclear follow avalon bus. Who want to use the IP core of friends altera help
ethmac
- ethmac IP CORE VHDL IN QUARTUS-ethmac IP CORE VHDL IN QUARTUSII
spi
- SPI IP CORE Verilog quartus-SPI IP CORE Verilog quartusii
uart
- uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
i2c_master_slave_core_latest.tar
- IIC IP核,可以直接集成在SOPC中的(⊙o⊙)哦-基于Quartus II 可直接集成到SOPC,自定义II C IP核
fft256
- quartus ii 中利用ip核生成fft模块,实现256点fft功能-quartus ii the use of nuclear generation fft ip module to achieve the 256 point fft function
FFT-IP-CORE--of-Quartus
- Quartus中fft ip core的使用一点心得,希望对大家有所帮助。-The Quartus fft the ip core to use a little experience, we hope to help.
the-use-of-Quartus-and-IP-core
- QuartusIP核的使用,很适合初学者使用-the use of Quartus and IP core
fir-ip-vhdl
- altera quartus fir ip核 vhdl程序 含测试文件-altera quartus fir ip nuclear vhdl program including test files
Altera.QUARTUS.II.Megacore.IP.Library.V7.2.SP2-SH
- Torrent to get a library of files which contains crack for Quartus II v7.2
ROM_test
- 使用quartus调用ROM的IP核,并生成激励文件进行仿真(Use the quartus call ROM IP kernel, and generate incentive files for simulation.)
cpu_uart_leds_ip
- 基于Altera 的一个IP核,能完成串口收发,以及自定义IP,可以作为自定义AXI总线接口的例子(Based on Altera's IP core, to complete the serial transceiver, as well as custom IP, as a custom AXI bus interface example)
HEX2MIF
- QUARTUS II SRAM/ROM初始化需要的HEX文件与Keil产生的HEX格式不同;该Modelsim程序,将Keil产生的Hex转换成,Quartus可以是识别的MIF格式;(The QUARTUS II SRAM/ROM initialization needs HEX files which are different from those generated by Keil. The Modelsim program converts Hex generated by Keil
PLL
- 本次的设计主要任务是学会调用锁相环 IP 核,并对其进行仿真, 具体要求如下:(1)熟练掌握调用锁相环 IP 核的详细步骤。将 50M 的时钟分成 20MHz 和 100MHz 两个时钟(2)对锁相环进行仿真,验证 调用的锁相环的正确性。(The main task of this design is to learn to call the phase-locked loop IP core.)