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Chapter-8
- 练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
view_quartus_simu_on_matlab
- 在进行Quartus仿真时，由于直接用自带的仿真工具无法查看正弦波，将仿真数据另存为tbl格式，用Matlab的程序调用该tbl文件，即可观察波形。当然，利用Modelsim更好。-During Quartus simulation, waveform directly with their own simulation tools can not view the sine wave, Save the simulation data for the tbl format, using the
Quart..
- 本学习主要是学习quartus调用modelsim 进行仿真的实验视屏-This study is mainly to learn quartus to call Modelsim simulation experiment VDT
m_sequence
- 用verilog语言描述了M序列（伪随机通信）的编码、解码、纠错等功能，本人通过了Quartus II 以及Modelsim的仿真。-Verilog language descr iption of the M sequence (pseudo-random communication) encoding, decoding, error correction, I passed the Quartus II and Modelsim simulation.
Example-b4-1
- 1. 定制一个双端口RAM，DualPortRAM 2. 在顶层工程中实例化这个RAM 3. 实现这个工程，在Quartus II仿真器中做门级仿真 4. 在ModelSim中对这个工程进行RTL级仿真 -Customize a dual port RAM, DualPortRAM On the top floor of the RAM engineering instantiation To realize the project, in Quartus II simu
Chapter2
- Chapter2文件夹：（1）Quartus II 8.0软件实例讲解：1位加法器实验，完整的设计工程文件在Chapter2/adder文件夹下（2)ModelSim SE 6.0软件实例讲解：十进制计数器实验，完整的设计工程文件在Chapter2/test_counter_10文件夹下 -Chapter2 folder: (1) the Quartus II 8.0 software examples to explain: an adder experiment, a complete
RS232
- （6）实验6：串口通讯实验，完整的设计工程文件在RS232文件夹下二、运行环境 程序在以下环境调试通过： （1）Windows XP； （2）Altera公司的Quartus II 8.0 for windows； （3）Altera公司的Nios II 8.0 IDE for windows； （4）Mentor公司的ModelSim SE 6.0；-(6) (2) Altera Corporation Quartus II 8.0 for windows Exp
shft_reg
- 移位寄存器的VHDL语言实现，quartus 和 modelsim 仿真-Shift register VHDL language quartus and modelsim simulation
clock
- 数字计时器的vhdl实现，quartus 和 modelsim 仿真-Digital timer vhdl achieve quartus and modelsim simulation
digital-watch
- 这是一个电子表的完整工程，仿真工具是modelsim，综合工具是quartus，开发版是DE2.里面含有文档进行详细说明-This is a complete electronic table engineering, simulation tools modelsim synthesis tool is quartus Developer Edition is DE2 which contains documentation for detailed instructions
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route
comprator_str_miley
- vhdl comprator and miley version that can simulate ans synthesis in all aoftwares like modelsim and quartus and ise
I2C_EEPROM
- 1. 本测试是夏宇闻 verilog数字系统设计教程，中的例程。 2. 编译环境Quartusii 3. 仿真环境Modelsim se 6.5d 4. 可综合部分已经经过quartus 验证正确 5. 仿真部分通过将I2C模块与一个EEPROM模型组合，通过时序仿真-EEPROM_I2C Verilog
CRC-5
- 用于RFID的CRC5模块，和相应的testbench，已在quartus和modelsim中进行功能验证-For RFID CRC5 module and the corresponding testbench, functional verification in Quartus and modelsim
verilogSerialcommunication
- FPGA实现RS-232串口收发的仿真过程（Quartus+Synplify+ModelSim）-On the RS-232 online asynchronous transceiver introduced a lot, recently there groping to do with the ModelSim timing simulation, combined with the online reference and their own thinking, do this thin
fpga
- 自己写的一个基于quartus ii12.0的一个建立工程及通过modelsim仿真的一个图文教程。提供大家参考。-To write a quartus ii12.0-based engineering and through establishment of a modelsim simulation of a graphic tutorial. Provide your reference.
ModelSim6.5bKeyGen
- ModelSim6.5b破解器。配合quartus ii9.1的官网ModelSim破解，已使用，确认正确-ModelSim6.5b Cracking unit。Proved right！
counter10
- verilog编写的10进制计数器，并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
ex1
- 设计一个循环灯控制器，该控制器控制红、绿、黄三个发光管循环发亮。要求红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒。（假设外部提供频率为1MHz的方波信号） 编程环境为Quartus II 11.0 仿真环境为 Modelsim 6.6d 通过仿真可以看出。系统复位后，红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒，三个发光管循环发亮。 -Design a loop lamp controller that controls the red, green and ye
zhilingyimaq
- 指令译码器电路的设计，包含具体程序和步骤，使用了QuartusⅡ和ModelSim软件。-Instruction decoder circuit design, including specific procedures and steps to use the Quartus Ⅱ and ModelSim software.