搜索资源列表
sdram
- sdram test controller altera
EP3C25EVM.rar
- cyclone III EP3C25 开发板原理图,包括flash, sdram, usb, ethernet 等接口电路，可作设计参考。,cyclone III EP3C25 development board schematic diagram, including flash, sdram, usb, ethernet interface circuit, etc., can be used for design.
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
SDRAM_ipcore_
- Altera SDRAM ip核详解-Altera SDRAM ip nuclear Detailed
tut_DE2_sdram_vhdl
- This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder.
AlteraSdramIP
- Altera Sdram IP 源码.rar-Altera Sdram IP source code. Rar
UP_IP_Library_80
- altera大学IP库，包含ps2、sdram、rs232等-altera University, IP libraries, including the ps2, sdram, rs232, etc.
CPU11111
- altera提供的sdram ip核例程，简单易懂。采用burst8模式。 -altera provided by the sdram ip core routines, easy to understand. Using burst8 model.
altera_avalon_sdram_slave
- Altera avalon sdram controller salve.
DE0_SDRAM
- DE0开发板SDRAM测试程序，10为拨码开关作为数据写入SDRAM中存储，在读出用7段数码管显示-ALTERA DE0 SDRAM
SDRAM
- 对SDRAM通信协议进行了介绍，而且比较详细，还包含了ALTERA的部分芯片-some information and descr iption about SDRAM
SDR_SDRAM_IP
- SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
test_sdram
- 对SDRAM进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等。工程基于altera的Quartus II 10.1进行设计，使用更高版本的软件均可。-SDRAM read and write for the project is divided into the internal PLL and reset processing module, SDRAM write logic block,
sdr-sdram-controller-source-code
- altera 公司sdr sdram 控制器源码，是VHDL的，大家选择下载-The altera sdr sdram controller source, the VHDL, we choose to download
SDRAM-design-FPGA-altera
- SDRAM design FPGA altera-SDRAM design FPGA altera.
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
sdr-sdram-verilog
- SDRAM IP CORE,ALTERA提供-SDRAM IP CORE,ALTERA
Altera-SDRAM_controller-IP-CORE
- Altera的SDRAM IP核代码，支持源码创作-Altera s SDRAM IP core code to support the creation of source
my_sdram_mdl
- 此功能为altera fpga 的sdram 控制器，串口接收与发送(This feature altera fpga sdram controller, serial port to receive and send)
sdr_sdram
- sdram使用接口仿真，altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)