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test_ddr2_ip
- ddr2 SDRAM 高性能控制器及测试-DDR2 SDRAM High Performance Controller
Design-and-implementation-of-High-Speed-Pipelined
- Design and implementation of High Speed Pipelined DDR SDRAM memory Controller
DE2_TV
- 本代码为Altera DE2开发板例程源码,(FPGA:EP2C35F672C6)quartus II 9.0以上可以编译(随板源码为7.2以下版本,在9.0以上版本编译会报错)。本代码实现一个音视频播放器TV_BOX。-This demonstration plays video and audio input a DVD player using the VGA output and audio CODEC on the DE2 board. There are two major bl
mem_interface_top_ddr_controller_0
- 在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。-DDR controller
STM32F746-FMC
- 这stm32f746代码描述了如何配置访问SDRAM控制器的FMC 记忆的低功耗模式(模式的SDRAM自刷新)。-This STM32F746 code describes how to configure the FMC controller to access the SDRAM memory.and low power mode (SDRAM Self Refresh mode).
DDR3-User-Guide
- 在DDR3内存控制器一起使用JESD79-3C符合标准SDRAM器件接口。内存类型,如DDR1 SDRAM,DDR2 SDRAM,SDR SDRAM,SBSRAM和异步不支持的回忆。在DDR3内存控制器,SDRAM,可用于程序和数据存储。梯形失真校正设备有一个实例。-Use JESD79-3C standard SDRAM DDR3 memory controller interface devices together. Memory types, such as DDR1 SDRAM, DD
sdr_ctrl_latest
- Code for use with windows on FPGA and provides latest controller for SDRAm and Flash at the same time