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shuzimiaobiao
- 用verilog实现了一个数字秒表的设计-verilog achieved using a digital stopwatch Design
paobiao
- 用verilog写的跑表程序--Stopwatch program written by verilog.
paobiao_gongyang
- 用verilog语言写的电子跑表,在共阳数码管上显示,八位的,初学EDA,感觉verilog语言好入门,我的QQ:942954258,欢迎与你共赢21世纪-Verilog language used to write electronic stopwatch, were positive in the digital display, eight, and novice EDA, started feeling good verilog language, my QQ: 942954258, w
paobiao.rar
- verilog实现的数字跑表 精确到10ms,verilog digital stopwatch to achieve accurate to 10ms
60seconds
- 60秒秒表设计,可暂停和分段计数等,所有功能是利用verilog HDL来描述,最后下载到CPLD/FPGA才能运行。-60 seconds stopwatch design, may be suspended and the sub-count
EXP4_sec
- 秒表 4个7数码管中的任何一个显示任意按键按下的次数。初始值为0,当计数到9时,下一次数值为0。利用Verilog HDL语言,编程实现上述功能。-Stopwatch
digitalpaobiao
- 用Verilog HDL语言编写的数字跑表源程序,已经通过综合编译及仿真。-With the Verilog HDL source code written in digital stopwatch has been through a comprehensive compilation and simulation.
clock
- 秒表的verilog语言实现,个人课程设计代码,已验证!实现显示秒,分,时暂停,修正等功能。-Stopwatch' s verilog language implementation, personal curriculum design, code, and has been verified! Implementation show seconds, minutes, suspended, amendment and other functions.
timer_set
- 这个是我自己编写的verilog代码,实现的功能是,在数码管上显示时间,按一个键,显示日期,长按一个键,显示秒表。。。时间日期可调-This is my own code written in verilog to realize the function of the digital tube display time, press a button, display the date, long press of a button, display Stopwatch. . . Time a
exer4
- 设计可以对两个运动员赛跑计时的秒表,verilog的大作业 -Design of the two athletes running the stopwatch timing, verilog great job
paobiao
- 用verilog 编写的数码管显示的秒表-Prepared using verilog digital display of stopwatch
paobiao
- 该程序是用verilog语言实现的数字跑表功能,其中分为计数模块与数码管显示模块。-The program is verilog language digital stopwatch function, which is divided into counting module with digital display module.
digital_clock
- 用Verilog HDL 设计一个多功能数字钟,包含以下主要功能: (1) 计时,时间以24小时制显示。 (2) 校时, (3) 跑表:启动、停止、暂停 -Verilog HDL design with a multi-functional digital clock, includes the following main functions: (1) time, time to 24-hour display. (2) school, (3) stopwatch: start
sclock_01
- verilog 秒表,利用视觉暂留,时钟频率-verilog stopwatch
stopwatch
- 基于Verilog的秒表设计,可以在modelsim与开发板环境中正常运行。-A stop watch program based on verilog
stopwatch
- Stop watch code in verilog
StopWatch
- verilog实现数字式秒表,秒表有一个按键开关:当电路处于“初始”状态时,第一次按键,计时开始(“计时”状态);再 次按键。计时停止(“停止”状态);第三次按键,计时器复位为 0’0’.0’’,且电路恢复到“初始”状态。详见压缩文件包内pdf说明。-Verilog in implementing digital stopwatch, stopwatches have a key switch: when the circuit is in the initial State, firs
stopwatch
- A stopwatch circuit that counts minutes and seconds, and has reset, pause functionalities. Designed using Verilog.
Stopwatch
- 在quatus平台,verilog语言编写的秒表代码。实现功能开始,暂停,复位,显示暂停。在Cyclone2上运行通过。-In quatus platform, verilog language stopwatch code. Achieve functional start, pause, reset, pause the display. On Cyclone2 run through.
miaobiao
- 秒表数码管实现,通过仿真验证,已下载到板子验证(The realization of the stopwatch digital tube)