搜索资源列表
rs_encoder
- RS编码器的fpga实现，有TESTBench-RS encoder to achieve the fpga, and TESTBench
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
GUI_Matting
- matlab编写的交互式image matting程序，包括：Poisson，Hillman，Ruzon等方法和源图像-matlab interactive image matting procedures, including: Poisson, Hillman, Ruzon methods and sources image
DDC
- 直接数字频率合成dds源码，cos三角函数生成代码，及测试代码，用于ddc前端测试的testbench。-direct digital frequency sysnthesis
BP062-BU-01000-r0p0-00rel0[1][1].tar
- AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
systemc
- Systemc实现一个加法器，一个乘法器，一个十选一器，并在testbench内检测其正确性。 适用于systemc入门。-Using Systemc for the realization of a adder, a multiplier, a decimator, and within a testbench for their functionalities . Designed for Systemc or C++ beginner .
softwaretest
- 浅谈软件测试流程,转自网络，有需要的可以看一下，写的不错-testbench or software test pipeline
cpu86model
- This is intel 8088 x86 IP core, contain software complier & modelsim testbench
cpu8088
- 8088 verilog 源代码，详见V代码以及TESTBENCH仿真
vani_tut
- A total of 52 files showing examples of shell scr ipting for Cadence NCSIM simulator, multiple single module + testbench examples in verilog 1995/2001, a "Randomized Smoothing Networks" paper (doc)+ppt+verilog codes and test bench from my EE7700 Dist
EDA
- VHDL上机手册（基于Xilinx ISE） ___________________________________________________ 1 ISE 软件的运行 2 创建一个新工程 3 创建一个VHDL源文件框架 4 输入VHDL程序 *5 仿真 6 创建Testbench波形源文件 7 设置输入仿真波形 -eda
fir
- 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
scrambleanddescrambler
- 适合802.11a的scrambler与descrambler的设计，适合OFDM系统设计的初学者，有testbench可供参考-The scrambler and descrambler for 802.11a design, OFDM system design for beginners, there are available for reference testbench
and_gate
- And gate testbench, testbench to simulate and run in modelsim
512
- several examples in Sram access in Spatan 3E
fifo
- 这个是我自己写的同步fifo ,供大家参考学习-this the syn-fifo,including testbench
i2c-IPcore
- i2c的完整可用的Verilog代码，包含testbench.-i2c complete Verilog code is available, including the testbench.
USB
- 用VHDL编写实现的USB接口控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the USB interface controller, bring their own testbench, after decompression project file can be opened with the ISE.
canbus
- 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.
PCI_testbench
- 基于FPGA的PCI接口源代码及Testbench Verilog程序代码-PCI_verilog_with testbench.