搜索资源列表
verilog_testbench_preliminary
- verilog testbench preliminary,很有用的-verilog testbench preliminary, very useful
alu1
- alu,原程序及testbench,供初学者参考-alu, the original procedures and testbench and reference for beginners
memory1
- memory,原程序及testbench,供初学者参考-memory, the original procedures and testbench and reference for beginners
register19
- register,原程序及testbench,供初学者参考-register, the original procedures and testbench and reference for beginners
timing19
- timing,原程序及testbench,供初学者参考-timing, the original procedures and testbench and reference for beginners
i2c_slave_con
- 可以支持连续读写的i2cslave源码,很适合作为master的testbench来用-can support continuous reading i2cslave source, very suitable as a master to the use of testbench
cfft
- 参数化FFT源代码,点数和位宽可变,内附testbench和说明文档-parameters of the source code FFT, counting and variable bit-enclosing testbench and documentation
RISCMCU
- riscMCU的VHDL实现,内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
oc8051
- 8051的verilog实现,内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
FIFO_v
- FIFO的verilog实现,内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
TestBench_writing
- testbench书写规范格式的ppt教程
systemverilog
- systemverilog是新出现的一种高级硬件描述和验证语言,这里给出了一些书和文章还有使用vmm方法开发testbench的例子
s_fifo
- 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench
fifo
- 一个同步FIFO,包括testbench,
i2c
- I2C controller的源码,包括TESTBENCH在内,里面包含有EEPROM的behaving model,前些日子在本站下了一个EEPROM的behaving model,发现可能只是作者的初版,里面错误比较多,因此上传一个能编译拿过来就能用的环境。
testbench
- 一个自己编写的全数字锁相环及其测试向量,比较简单但功能基本达到。
core_arm.tar
- vhdl的arm核 包含testbench
guiden-to-write-efficient-testbench
- 这是一个xilinx公司发布的写testbenth的入门向导,指导我们快速高效的写自己的testbenth,从而改进我们的仿真效果。
testbench
- 32位除法器的测试程序, 由随机向量产生函数产生一组随机数 来验证计算书否正确
ddstest
- 实现dds的testbench,很有帮助