搜索资源列表
testbench_vantage
- 芯片设计验证测试技术方法，基于verilog语言-testbench for ASIC Design, Verilog
ASK0908272
- 自己写的二进制频移监控程序，包含testbench,供大家参考-this is the AsK programme,including testbench
E1Tsi_TB
- TSI testbench for E1
wave
- TESTBENCH OF CARDIO SYS-TESTBENCH
rs232
- RS232的串口控制器，本程序中的每个小模块都有与之对应的testbench，模块清晰，实现结构简单。很适合Verilog编程初学者来练习！-RS232 serial port controller, the program has a small module for each corresponding testbench, module definition, to achieve simple structure. Verilog programming is suitable for
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
cordic
- altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
I2C
- I2C总线接口的Verilog源码文件和modelsimd的测试文件-Verilog source code of I2C bus interface and testbench code of modelsim.
multiplier8x8
- 8位定点乘法器，支持有符号数/无符号数运算。采用4-2压缩树结构，并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
top1
- verilog可综合的图像旋转模块和testbench-verilog synthesizable testbench modules and image rotation
new_fifo
- 最新的testbench of FIFO ，使用Vmm，VCS，可以大致了解一下VMM的体系-the new fifo VMM testbench
Mealy
- mealay model with testbench
half_adder
- half adder with testbench
memoryarray
- 由VHDL撰写的两记忆体转置程序，内含testbench与转置源码。-VHDL written by the two memory migration procedures, includes testbench and migration source.
chuanbing
- 串并转换器的verilog源代码带testbench文件-String and converter verilog testbench file with the source code
counter
- 8bit counter testbench modeling source file
adder_4
- 详细介绍了四位加法器的verilog代码，还包括详细的testbench代码。-Details of the four adder verilog code, also includes detailed testbench code.
des
- des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
TB_VHDL(adder)
- 加法器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about adder for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
counter
- 计数器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about counter for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example