搜索资源列表
AHB_to_Wishbone_Verilog
- 该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
testbench
- 介绍如何编写verilog的仿真程序，很适合初学者-How to write verilog simulation program, it is suitable for beginners
rsa.tar
- good working RSA code with testbench
mppt_mod
- maximum power point tracking system (MPPT) VHDL code with testbench
Test
- verilog语言编写的分频程序及其testbench测试文件。fpga开发入门的好例子。-verilog divide written test procedures and testbench files. fpga development of entry-a good example.
test_bench_8bitserialadder
- testbench for 8 bit serial binary adder
verilogtestbench
- 关于verilog的testbench资料文档，通过文档可以更好的了解verilog的testbench的写法。-The testbench verilog information about the document, through a better understanding of the document to the testbench verilog is written.
AES_enc_core_tb
- this code discribers testbench for aes algorithm. it is written by .vhdl
booth-test-bench
- booth 乘法器的测试代码 booth testbench-booth multiplier test code booth testbench
ALU
- VHDL实现ALU的源代码，并且提供了一个详细的testbench-ALU VHDL source code implementation, and provides a detailed testbench
m_m
- 这是我写的一篇论文中关于m序列及M序列的源代码及各个模块所编写的testbench。各个模块编写正确，有关爱好者可以在之上进行扩展。-This is a paper I wrote on the m series and M series, and each module source code written testbench. Preparation of each module correctly, the lovers can be extended over.
stopwatch
- 成一个具有闹钟功能的时钟电路设计。并编写Testbench对电路功能进行验证。-stopwatch with alarm function
dac
- Delta sigma DAC for use in FPGA includes Testbench
verilog
- 这是一个uart串口实现16550的实现，代码已测试过了。-This is a 16550 uart serial port, the code has been tested before.
Viterbi_Verilog
- viterbi译码的verilog实现,提供相应的原程序代码和testbench -viterbi decoder verilog implementation
ssram-and-tesebench
- 实现一个256x8的同步静态存储器SSRAM，用硬件描述语言Verilog写的，同时谢了测试程序-it realized a 256x8 SSRAM,writen by Hardware descr iption language Verilog ,and include the testbench.
fp_prj
- 简单的Testbench设计，对FPGA初学者来说很好用-Simple Testbench design, the FPGA is fine for beginners
VHDL_Somador8Bits
- * FullAdder implementation in VHDL with respectives signals: a, b : in std_logic_vector (7 downto 0) soma : out std_logic_vector (7 downto 0) ci : in std_logic co : out std_logic overflow : out std_logic negativo : out std_logic
lab1a
- 这个是一个简单的VHDL testbench程序，让你简单清楚的了解如何写一个testbench-this is a simple vhdl testbench program, it is very easy for you to understand how to write a testbench program
SystemVerilog
- SystemVerilog 是一个硬件测试语言。可以搭建测试平台。本书有很多的测试用例。并且会告知你如何使用该语言。-SystemVerilog for Verification A Guide to Learning the Testbench Language Features Second Edition