搜索资源列表
xuliejianceqi
- 序列检测器00101，包括源代码，testbench，ise13.4测试以及综合通过等说明文档。-Sequence detector 00101, the state machine verilog, testbench, ise13.4 simulation map. The test is successful
core
- 串转并的电路转换器，并包含testbench。-The converter circuit about serial to parrel, including testbench.
RS422_UART
- RS422 串口通讯 （包括 testbench，虚拟RAM，数据收发，波特率生成，数据接收抗干扰）-RS422 UART testbench BaudGen
uart
- 这是一个串口通讯模块，从串口接收14个数据后用于计算并将计算结果从串口发送出去，里面包含testbench。-This is a serial communication module 14 the serial port to receive data used to calculate the results and sent the serial port, which contains the testbench.
ADF4113_loader
- ADF4113 loader written on Verilog + Icarus Verilog testbench
eetop.cn_pll_integer_N
- 整数锁相环的malab 建模与仿真程序 用于行为及的验证与仿真 对PLL建模有好处-simulink of integer PLL simulation model and testbench
serial-cordic-verilog
- implementation of cordic algorithm for many aplication like cos, sinus, polar to rectangular conversion and rectangular to polar conversion. It s written in verilog language and testbench is included
Verilog-code-for-finding-GCD
- State machine implemented in verilog to find GCD of two 8 bit numbers. Two files are included (module and its testbench)
FSKaPSK
- FSK&PSK编码，可以通过testbench仿真-FSK & PSK coding, you can testbench simulation
32bit_multiply
- 包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。-Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementat
half_adder
- 半加器的VHDL实现，包括Testbench的编写，可供新手参考-Half Adder VHDL Testbench
ic74f539
- ic74f539芯片的VHDL实现，包含Testbench编写，可供新手参考。-ic74f539 VHDL Testbench
ic74hc574
- ic74hc574芯片VHDL功能实现，包括Testbench编写，可供新手参考。-ic74hc574 VHDL Testbench
testbench_verilog
- Verilog语言中的testbench的语法教程，可供参考，分享分享-Verilog language in the testbench grammar, reference, share
Multiplier
- 我是2014级复旦的研究生。这是用VHDL语言设计的任意的M乘以N位的乘法器。设计中，被除数和乘数的位数是通过参数来设置的，可由你来修改。我已写好了testbench。可放心使用。-I am a 2014 graduate of Fudan University. This is an arbitrary M VHDL language designed by N-bit multiplier. Design, the dividend and the median multiplier is
Example-b8-1
- 使用ModelSim对Altera设计进行功能仿真的简要操作步骤 1.建立仿真工程 2.Altera仿真库的编译与映射 3.编译HDL源代码和Testbench 4.启动仿真器并加载设计顶层 5.打开观测窗口，添加信号 6.执行仿真-Using ModelSim Altera design for functional simulation brief Procedure 1. Create a simulation project Compilation and map
Example-b8-2
- 使用ModelSim对Altera设计进行时序仿真的简要操作步骤 1.建立工程，设置仿真工具选项参数 2.使用Quartus II编译工程 3.建立仿真工程 4.Altera仿真库的编译与映射 5.编译HDL源代码和Testbench 6.启动仿真器并加载设计顶层 7.打开观测窗口，添加信号 8.执行仿真-Using ModelSim Altera design for timing simulation of brief steps 1. Establish pro
CAN
- 包含CAN协议讲解与CAN协议控制器的verilog实现(含有testbench），该实现模仿SJA1000架构，接口完全一致。压缩包中还包含SJA1000的手册与应用指南，非常好的CAN学习资料。-CAN protocol controller implemented in Verilog（contain testbench） & instruction of CAN protocol & datasheet and user manual of SJA1000
nand_controller
- this the nand flash controller having testbench and simulation model for nand flash in it-this is the nand flash controller having testbench and simulation model for nand flash in it
registerbank
- THIS file consists of register bank and its testbench