搜索资源列表
MUX41
- 四选一的选择器 FPGA源码,包括模块Verilog文件和测试testbench文件-Four one of the selector FPGA source code, including the module Verilog files and test testbench files
ADDR
- 8位全加器,包括半加器verilog文件,全加器verilog文件,8位全加器verilog文件,和8位全加器测试testbench文件-8 full adder, including half adder, full adder Verilog file, Verilog file, 8 full adder Verilog files, and 8 full adder test testbench file
simProcessorEx
- 一个简单微处理器内核的VHDL程序,包含源代码(位于Source目录内)及ModelSim仿真代码(位于testBench目录内)。使用该内核进行一个功能验证程序(位于simProc_test目录内)-a simple processor core program and test code based on VHDL language
boxingfashengqi
- 波形发生器的源代码,有正弦波,三角波,锯齿波,方波。modelsim仿真,包含testbench仿真代码,testbench用的verilog编写,波形发生器源代码用的VHDL编写。-Waveform generator source code, sine, triangle, sawtooth, square wave. modelsim simulation, testbench simulation code contains, verilog write testbench use, w
ima_adpcm_encoder_latest.tar
- This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by def
Privite_rom_32_20160519
- xilinxFPGAROM32*1原语的使用,vivado工程,含有仿真测试文件Testbench,添加地址寄存器,能够按址寻找你所存储的数据,仿真一目了然,对初学者甚好,verilog语言实现该功能。-xilinxFPGAROM32* 1 primitive use, vivado engineering, simulation test file containing Testbench, add an address register, Anzhi can find the data yo
sequence_detector
- verilog之序列检测,vivado工程,使用状态机的方式检测任意长度的数据顺序,提供四个检测工程,并全部带有Testbench,保证你能方便的学会序列检测这个知识点。-Data in a sequential manner to detect any length of sequence detection verilog, vivado engineering, using a state machine provides four detection project, and all w
FIFO_TEST
- XILINX FIFO IP核测试程序,已经通过测试,方便可用-XILINX FIFO IPcore testbench
CLA_20
- 用verilog语言编写的CLA_20文件。CLA_20是20位超前进位加法器的源代码,该代码验证后功能正确,读者可以自行编写testbench代码进行验证。-With verilog language CLA 20 files. CLA 20 is 20 lookahead adder source code after the code verification function correctly, readers can write their own testbench code fo
CLA_4
- 用verilog语言编写的CLA_4文件。CLA_4是4位超前进位加法器的源代码,该代码验证后功能正确,读者可以自行编写testbench代码进行验证。-With verilog language CLA 4 files. CLA 4 is a four-ahead adder source code after the code verification function correctly, readers can write their own testbench code for ver
qpsk
- QPSK调制程序的testbench程序 timescale 1ns/1ns //单位时间,时间精度 module qpsk_tb //qpsk调制的testbench reg clk reg rst reg x wire y -QPSK modulation program testbench program timescale 1ns/1ns // unit of time, time accuracy module qpsk_tb // qps
chuzuche
- 出租车vhdl程序,并带有testbench仿真程序,通过开始按键复位,然后根据行使信号进行公里计数,起步价3公里8元钱,超过3公里一公里1元钱-Taxi vhdl program, with a testbench simulation program, started by the reset button, then the exercise kilometer count signal, starting at 3 km 8 yuan, more than three kilometer
inout
- 用于RAM的测试文件,以及testbench-some RAM testingfiles,and its testbench
adder_carry_chain
- 使用verilog语言实现进位链加法器,quartus下编译,并使用modelsim进行了验证,内含carry_chain.v代码文件以及testbench文件-use verilog language,carry_chain adder
Vhdl_testbench
- vhdl 的testbench编写教程,英文ppt以及源码工程-Write tutorials, as well as English ppt Source of engineering vhdl testbench
DES-Verilog-master
- DES加密算法硬件verilog实现,包含testbench,加密主模块encrypt,明文变换模块LRToCiphertextConverter,NextRi模块等子模块。-DES encrypt verilog
apbtoaes128_latest.tar
- AES加密算法verilog代码实现,基于APB总线接口数字IP,包含详细的testbench-AES encryption algorithm verilog code, based on the APB bus interface digital IP, contains a detailed testbench
apbi2c_latest.tar
- APB总线协议转I2C总线协议的接口IP,verilog代码实现,包含详细testbench-APB bus interface to I2C bus interface IP,verilog code
UART-master
- UART通讯接口verilog代码实现,uart_tx子模块和uart_rx子模块,包含详细testbench-UART interface verilog code, uart_tx、uart_rx, testbench
gpio-master
- 基于WISHBONE总线接口的GPIO模块verilog代码实现,包含详细GPIO定义文档,testbench,RTL仿真与综合环境-WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn