搜索资源列表
testbench.sv
- RS 编码和解码Verilog Code, 实现了RS（544,514)的编码和译码；--RS Coding and Decoding Verilog code， implement RS（544,514)
ddr_controller
- 完整的DDR控制器设计，包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.
memTB
- it is a testbench describing the function of a memory
VHDL_4bit_magnde_compar_code_testbench
- this a vhdl testbench for a 4 bit magnitude comparator that comprises all the stimuli a 4 bit magnitude comparator function table.-this is a vhdl testbench for a 4 bit magnitude comparator that comprises all the stimuli a 4 bit magnitude comparator
double_addsub
- 双字的加减法的verilog源代码和testbench，已经过测试-verilog source code and testbench double word addition and subtraction, and has been tested
pipeline_add
- pipeline式累加器的verilog代码和testbench文件，已验证-pipeline type accumulator verilog testbench code and documents, verified
gray_counter
- altera官方格雷码计数器的verilog代码和testbench,已测试-altera official Gray code counter verilog code and testbench, have been tested
usb_latest.tar
- This is USB zip file which has a master and slave configuration. there are different modes inwhich it can work. There is testbench module as well which helps in identifying whether design is working correctly or not.
UART_TX
- FPGA串口发送测试程序，包含按键模块，串口发送模块，和串口模块的testbench文件-FPGA serial port test program, including testbench file button module, serial sending module, and the module' s serial
4-bit-comparator-with-testbench
- 4 bit comparator test bench
fifofinal
- FIFO verilog学习时的基础编程练习。以8位输入，8位输出为例，输入输出采取不同时钟。 附加testbench。-first in first out
AWGN_VerilogDesign-master
- 加性高斯白噪声生成的VERILOG实现，包含所有的testbench文件。可直接使用-Additive white gaussian noise generated VERILOG realized, including all testbench files. Can be used directly
TB_Read_Write_File_vhd
- Simplified VHDL testbench: Read/Write from/to Text File.
CCIR656-encoder
- a source code of CCIR656 encoder in verilog HDL with corresponding testbench and a snapchat of the resulting waveform-a source code of CCIR656 encoder in verilog HDL with corresponding testbench and a snapchat of the resulting waveform
16Bit-Group-Ripple-Adder
- Verilog Testbench for 16Bit Group Ripple Adder
fpga123456
- 从一个网友哪里找到的，Verilog十大基本功2（testbench的设计 文件读取和写入操作 源代码）-From a user where to find, Verilog ten basic skills of 2 (testbench design documents to read and write the source code)
UART_TX
- verilog写的串口发送程序，具有单字节发送和多字节发送功能，附带testbench，可自行验证-verilog write serial transmission program, sending a single byte and multi-byte transmit function, with testbench, can verify their own
UART_RX
- 自己用Verilog写的串口接收程序，有testbench，可实现单字节接收和连续接收，testbench可测功能-Own use Verilog write serial reception procedures, testbench, can achieve single-byte receive and continuous reception, testbench measurable function
sdram_test
- 在vivado中用于测试SDRAM，DDR3学习比较有帮助-the testbench for ddr3
soda_machine_mealyamoore
- soda_machine的一个有限状态机，用verilog描述，分别有moore和mealy,还提供了testbench.-soda_machine of a finite state machine, with verilog descr iption, respectively, moore and mealy, also provides a testbench.