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比较器的测试矢量
- 一个很好的testbench的例子。
sha-1.rar
- 本算法基于leon2协处理器接口标准,内含testbench,在modelsim中仿真通过,在ise9.2中综合及后仿真通过。,The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
FPGA-PCI.rar
- 基于FPGA的PCI接口源代码及Testbench Verilog程序代码,fpag pci
8051单片机源码verilog版本
- 8051单片机源码verilog版本 包括rtl, testbench, synthesis ,Verilog source code version of 8051, including rtl, testbench, synthesis
Chapter10
- 第十章的代码。 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
mp3decoder
- verilog实现mp3解码程序,包括testbench-mp3 decoder verilog implementation procedures, including the testbench
Am29lv160d
- 在逻辑的系统仿真中使用的FLASH模型(AMD的Am29lv160d),包括VHDL代码文件和verilog代码文件和testbench,并且有相应的pdf说明文档。-In the logic system used in FLASH simulation model (AMD s Am29lv160d), including VHDL and Verilog source code files of documents and testbench, and the corresponding
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
VERILOG-jpeg
- 用Verilog语言在FPGA上实现JPEG图片的解码,附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
Flash_ctrl_vhdl_tb
- VHDL编写的flash控制器源代码.包含testbench。-Prepared by flash controller VHDL source code. Contains testbench.
32bit_RISC_CPU
- 32 risc cpu的参考设计,内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
custom_cordic
- verilog编程开发的cordic例程,计算SIN,COS功能与计算幅值角度功能可设定,运算宽度可设定,并有完善的TESTBENCH。-Verilog programming developed CORDIC routines to calculate SIN, COS function and calculating the amplitude of the perspective of function can be set, computing the width can be set,
AVR_Core.tar
- vhdl语言编写的AVR单片机IP核,里面有testbench和说明文档。-VHDL language AVR Single Chip IP core, there are Testbench and documentation.
XiaYuWen_8_RISC_CPU
- 夏宇闻8位RISC_CPU的完整代码+TESTBENCH(已调试) modelsim工程文件,包括书中所测试的三个程序和相关数据,绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的,只有一个mcu的代码,但很多和书中的是不一样的,自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方,如clk_gen.v中clk2,clk4是没有用的,assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的,会使时序恶
code
- 一个8位微处理器的VHDL代码以及testbench-8-bit processor VHDL
i2c_core
- I2C core 及testbench(verilog)-I2C core and testbench [verilog]
rs-codec-8-16
- RS[255,223]纠错码verilog源码,包含编码和解码模块,以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
fifo1
- 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
pcie_vera_tb_latest.tar
- FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number
ima_adpcm_encoder_latest.tar
- This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by defau