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Simple_TOA
- This a simple position location algorithm using Least Square Estimation algorithm. Timing information is time of flight (TOA) of signal between Tx and Rx. This code generally describes the Positioning method, Also it plots final coordinate of node in
alarm-clock
- 该代码用VHDL实现了闹钟的定时和提醒功能。里面包含四部分代码，分别实现了60，30，2分频；键盘控制；外围控制；用quartus2软件就可以打开，压缩包中附有四个代码的仿真结果。-The VHDL code used to achieve the alarm clock to remind the timing and function. Code which contains four parts, namely a frequency 60,30,2 keyboard control
7822
- 7822读写时序 7822读写时序 -7822 read 7822 read and write timing timing timing 7822 read 7822 read and write timing
51shiyongC
- 44键盘C51单片机程序,51单片机的软件复位程序,单片机IO驱动74LS164的C51程序,单片机T2定时器实现1秒精确定时程序,单片机做的AD转换程序( adc0809程序 ),电子钟程序,流复杂一点的水灯程序-44 keyboard C51 single-chip procedure, 51 single-chip software reset procedures, single-chip IO driver 74LS164 procedures of the C51, single-c
NoteBook
- 有关记事本的代码，文件编辑打开查看帮助时间记录等功能-Code on the Notepad, open the View Editor to help document the timing of the recording and other functions
project4
- 定时计数器,只是基于C51单片机的一小段程序，可以实现机器计时和仿真计时同时进行。-Timing counter, only a small section of single-chip based on the C51 process, can be achieved time and simulation time machine at the same time.
deCPLDVHDLshijong
- 基于CPLD的VHDL语言数字钟（含秒表）设计 利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。 本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。 -CPLD based on the VHDL language di
Altera_timing
- 本文件讲述了Altera的FPGA的时序原理-This document describes Altera' s FPGA timing principle
danpianjikeshe)
- 实现电脑时钟，闹钟，精确定时等功能挺不错的，大家看看吧-The realization of the computer clock, alarm clock, precision timing and other functions of very good, let us look at it
002
- 时序灯，利用平铺顺序结构实现几个灯的时序点亮。-Timing lights, the use of tile order of the structure of the timing to achieve a number of lights lit.
yongcic
- 永磁交流真空接触器的线圈控制单片机源程序，供大家参考学习，理解永磁开关是如何控制的时序问题。-Permanent magnet AC vacuum contactor coil of single-chip microcomputer to control the source code for your learning, understanding how to control permanent magnet switch is the issue of timing.
ASIA_GAME_design
- 需求规格包含了——系统需求分析、用例图 概要设计包含了——系统架构设计、架构描述、架构图、部署图、时序图 详细设计包含了——系统详细设计、类图、数据库设计、ER图 中间信息包含了所有用过的图例，图表 uml.mdl是使用Rational创建的建模文件-Requirements specification contains a- System Requirements Analysis, Use Case Diagram Contains a summary of
temperatureclock1602display
- 温度传感器18b20，单片机内部定时时钟，1602液晶显示（带protues仿真）-Temperature Sensor 18b20，Single-chip internal timing clock，1602 LCD display。（with protues simulation）
dpjdzz
- 一个单片机的用汇编语言编的电子钟的程序，可以完成基本的LED显示的调时，分，和正常计时的程序-A single chip using assembly language for the electronic bell procedure, you can complete the basic tune of the LED display hours, minutes, and normal timing of the procedure
i2c_lcd
- 介绍了用ＤＳＰ２８１２的ＩＯ口，模拟出Ｉ２Ｃ的时序，然后与视频驱动芯片通信-DSP2812 introduced by the IO port, I2C timing simulation, and then with the video driver chip communication
Significant6-digitfrequencycounter
- 6位数显频率计数器，利用AT89S51单片机的T0、T1的定时计数器功能，来完成对输入的信号进行频率计数，计数的频率结果通过8位动态数码管显示出来。要求能够对0－250KHZ的信号频率进行准确计数，计数误差不超过±1HZ。-Significant 6-digit frequency counter, using AT89S51 MCU T0, T1 timing counter functions to complete the input signal frequency counting,
all_packages_20080525.tar
- FMF VHDL Models All the FMF models are VHDL 93 and VITAL 2000 compliant and require the VITAL 2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We hav
CSharpgetTime
- C#高精度记时度，用API函数实现的高精度记时器，可以达到微秒级别，可用于测试-C# High-precision timing, the use of API functions to achieve high-precision timer, you can achieve microsecond level, can be used to test
sd_make
- SD_驱动制做资料： 有程序,时序图，SD制做总结．-SD_ drive makes material: A program, timing diagram, SD making summary.
d1
- 实现单片机控制电子表的定时功能。为汇编语言程序。有报警的功能。-The realization of single-chip microcomputer to control the timing of electronic form. Procedures for the assembly language. Have alarm functions.