搜索资源列表
FPGA-Timing-Function-Model-Analysis_1
- IR Drop Analysis and Timing-Function Model Generation for Embedded FPGA(I).
FPGA-Timing-Function-Model-Analysis_3
- IR Drop Analysis and Timing-Function Model Generation for Embedded FPGA(III).
QuartusIITimequest
- 关于quartus中的Timequest Timing analyzer的讲解PPT，由Altera提供-About quartus in Timequest Timing analyzer' s explanation PPT, provided by the Altera
10[1].1.1.66.2227
- In this paper, we present a novel data-based method for simultaneous Maximum Likelihood (ML) symbol and carrier-frequency o畇et estimation in Orthogonal frequencydivision multiplexing (OFDM) systems. Statistical properties introduced by the cyclic
PrimeTime_Advanced_Timing_Analysis_User_Guide
- PrimeTime Advanced Timing Analysis User Guide
Delphi.timing.data.into.design.code
- Delphi定时数据导入设计代码Delphi timing data into the design code -Delphi timing data into the design code
Delphi.timing.module.development.design.code
- Delphi编程定时模块开发设计代码Delphi Programming timing module development and design code -Delphi Programming timing module development and design code
VB.code.modular.programming.network.timing
- VB模块化编程网络计时代码VB code for modular programming network timing -VB code for modular programming network timing
synchronization
- GARDNER algorithm used the timing of the simulation module, enter each symbol four sampling points, by interpolation, the output value of one sample
VESA-timing_dmt(NEW)10
- 介绍VESA标准显示屏监控时序，详细介绍分辨率，行，场频率-This document includes all current VESA Monitor Timing Standards & Guidelines. Guidelines are subjected to the same VESA review and approval process as Standards , but are designated as Guidelines to ease concer
timing
- Provides functions for timing algorithms
TimingController
- 能够实现 LCD时序驱动,通常cpu送出的信号为data bus信号，液晶屏幕并不能正常显示，需要lcd driver-LCD timing controller, usually cpu send out the data bus signal, so the lcd driver can t display normally, need the driver
modelsim-timing-analysis
- 自己整理的一个关于如何使用modelsim进行功能仿真，时序仿真和布局布线的后仿真的文档，例子是抄的，针对的版本是modelsim se6.2b-Their finishing a feature on how to use modelsim for simulation, timing simulation and post-layout simulation of the document, copy the example is for the version of modelsim se
1ms-timer-timing-B
- MSP430F149的定时器B产生大约1ms的定时，使主程序退出低功耗模式。主程序执行一遍流程，再次进入休眠，等待下一次被唤醒。中断TIME_FA次后，改变定时器的定时时间。每次中断的时候翻转P4.1脚的电平，使LED熄灭或者点亮。-MSP430F149 generate approximately 1ms timer timing B, the main program to exit low-power mode. Main program execution once the proces
Aer
- 一种改进的时钟定时抖动估计方法An improved estimation of clock timing jitter-An improved estimation of clock timing jitter
Ward-Calling-System_-timing-_latch
- 病房呼叫系统 锁存器 计时模块 优选模块 时间模块-Ward calling system timing module latch time module selection module
gcc-timing
- ibm cell芯片编程，使用gcc交叉编译器实现定时功能的代码。-ibm cell chip programming, using the gcc cross-compiler to achieve timing code.
HC11-timing
- hc11 timing source code and simulation in Verilog program
The-timing-of-track-and-field
- 设计一个比赛日程安排表，使得在尽可能短的时间内完成比赛。-The timing of track and field
timing-marquee
- 自己在做课程设计的时候做的一个简单的定时跑马灯程序。-A simple timing marquee program.