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gray
- 灰度投影算法的verilog代码，有图，成功的仿真 -gray project verilog
CPLD-Three-voting
- CPLD/FPGA 设计实例手册 用VHDL语言设计三人表决器 用原理图输入的方式设计三人表决器 用verilog-HDL语言设计三人表决器-CPLD/FPGA design example manual Three of the voting machine VHDL language Schematic design of a three-member voting Verilog-HDL language design three-member voti
hdb3verilog
- 实现基于verilog语言的HDB3的编玛功能 有截图和代码解释 -HDB3 encoding
calendar
- 这是用Verilog写的万年历，里面包含的日月年各个模块。各个模块用Verilog写的，最后用原理图把各个模块组装成最终的系统。每个模块经过仿真没有问题，整个工程在板子上经过试验，能够完成万年历的功能。-This is the calendar write with Verilog, contains the sun and the moon years each module. Each module in Verilog written, finally the principle diag
EDA
- Quatus下用Verilog语言编写的双向交通灯控制系统，内含程序及波形图，注释详细，课程设计-Verilog language Quatus two-way traffic light control system, containing program and waveforms, detailed annotations, curriculum design
DDR_check
- altera公司cycloneII 2c35开发测试DDR的verilog代码，带仿真波形图。-altera cycloneII 2c35 verilog code development and testing DDR, with simulation waveform.
CPLD-code
- CPLD开发板实验代码，包括Verilog和VHDL源代码，原理图-CPLD development board experimental code, including Verilog and VHDL source code, schematics
Quartus_II-training-file
- Quartus 培训和使用教程，包括使用原理图输入，使用Verilog建立工程等-Quartus training file，include usingthe schametic to create project,and use the verilog file to create the project.
q_74ls138
- 在quartus II 9.1上用verilog原理图形式实现的74ls138功能的38译码器-38 of 74ls138 features achieve verilog schematic form in quartus II 9.1 decoder
clock
- Quartus II软件设计数字电子钟，使用verilog语言编写各个 模块生成symbol files，再用原理图方式制作顶层文件。 完成的功能有：能够显示时、分、秒；具有清零，调节分钟的功能； 具有整点报时功能，声响电路发出叫声； -failed to translate
lab-2-Memery-design-with-VerilogHDL
- 用verilog 编写的32位存储器代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-32-bit memory code written in verilog, through modusim simulation, including the principle diagram and code, in the form of a lab report write
3-8-decoder
- 三八译码器,用Verilog HDL语言描述，包含文件说明以及波形截图-3-8 decoder using Verilog HDL language descr iption, including documentation and waveform capture
8-1-mux
- 八选一数据选择器，Verilog HDL语言描述，包含文件说明和波形截图-8-1 MUX, Verilog HDL language descr iption ， contains the file descr iption and waveform capture
10010sequece-detector
- 序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-Sequence generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
M=15generator
- 模15序列发生器，Verilog HDL语言描述，包含文件说明和波形截图-mod15 generator, Verilog HDL language descr iption , contains the file descr iption and waveform capture
voter
- 少数服从多数表决器，Verilog HDL语言描述，包含文件说明和波形截图-Majority voter, Verilog HDL language descr iption, contains the file descr iption and waveform capture
ds_test12
- 在Verilog语言下用FPGA驱动DS18B20，带数码管显示，带LED报警，有报警值调整功能。这个是本人调过的，原版调通代码没改的，绝对能跑通。建议用QuatusII全编译后看一下RTL图就能理解程序是怎么工作的。-A Demo of DS18B20 on FPGA.
sig_control
- 交通信号灯的verilog实现，里面包含有源程序和仿真图。-Verilog realize traffic lights, which contains the source code and simulation diagram.
erzhihuaxingtaixue
- 用verilog编写的，可以将灰度图转换成黑白的二值图，阈值已经设置好-gray to Binary
ADC0809
- ADC0809的verilog实现 及仿真的文件 和仿真的波形图-ADC0809 implementation and simulation of verilog files and simulation waveforms