搜索资源列表
DIG_LED
- 数码管的Verilog HDL高级描述,将数码管接口封装完成,适宜20MHz的时钟使用-Digital control of high-level Verilog HDL descr iption of a digital control interface, complete package, suitable for use 20MHz clock
timer
- verilog秒表fpga 4位数码管显示-verilog digital display stopwatch 4
source
- FPGA驱动八位数码管,做为16进制计数器。-16 counter,using verilog HDL
electric_timer_qutus
- 用verilog语言编写,主要是在FPGA中实现一个简易电子表的作用,利用时钟实现控制六个数码管的显示-With verilog language, mainly in the FPGA the role of a simple spreadsheet, use the clock to achieve control of six digital display
AT24C04VHDL
- 用Verilog HDL语言编写的AT24C04程序,并用数码管显示,已经过测试,很好用。-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use.
verilog4
- 用verilog语言编写的数码管显示实验程序。通过分频计数来使数码管以640ms间隔从1变化到F。压缩包内也包含此数码管显示实验程序的modelsim仿真文件。-Verilog language with digital display test program. By dividing the clock count to make the digital control to 640ms intervals from 1 to F. This package also contains a
qiangdaqi
- verilog hdl实现的三路抢答器,一个复位键,八个数码管,五个LED灯,晶振为12 MHz 采用CPLD 器件为ALTERA 的EPM7064SL-44芯片 -verilog hdl implementation of three-way Responder, a reset button, eight digital control, five LED lights, crystal is 12 MHz ALTERA CPLD device is using the E
qiangdaqilunwen
- verilog hdl实现的三路抢答器,一个复位键,八个数码管,五个LED灯,晶振为12 MHz 采用CPLD 器件为ALTERA 的EPM7064SL-44芯片 -verilog hdl implementation of three-way Responder, a reset button, eight digital control, five LED lights, crystal is 12 MHz ALTERA CPLD device is using the E
Nixie-tube
- 这是一个verilog HDL语言代码,主要利用状态机控制数码管,从0到9循环显示。-This is a verilog HDL language code, the main use state machine control digital tube, from 0 to 9 cyclic display.
digitron_driver_V
- 关于easy fpga开发板的led数码管的驱动; 此为verilog程序 --输入:控制端ctrl_digin[2:0]共三位,表示(0~7)控制8个数码管的选通, -- 数据端dig_dtin[3:0]共四位,表示(0~F)控制数码管显示的数字 -- 控制时钟clk_dig一位用于时钟同步 --输出:显示dig_dtout[6:0]共七位,控制A,B,C,D,E,F,G[6:0]小数点不包括在内; -- 控制位ctrl_digout[7:0]共八位,任意时
tube_driver
- 利用altera公司的FPGA使用verilog语言描述了数码管的驱动电路以实现数码管显示功能-Altera FPGA verilog language descr iption of the digital control drive circuit to digital tube display
freq_detect
- verilog写的数字频率计,用七段数码管显示-verilog to write the digital frequency meter
bin27seg
- 数码管的verilog的详细描述和解释,很有利于学习。-seven segments
ssd
- 一个fpga开发板上的数码管应用,是用verilog编写,已经在开发板上-a SSD practice
ds1302_seg7
- ds1302的verilog驱动,数码管显示-ds1302 s Verilog-driven, digital display
JTD
- 基于verilog的交通灯,倒计时并具有动态显示功能。红灯结束后黄灯闪烁5s,stop为高电平时,数码管闪烁并禁止通行-traffic light with a function of displaying and counting.
7_SEGMENTLED
- 在DE2开发板上,通过在Altera QuartusII软件中编写.v代码,驱动DE2开发板上的7段数码管。-DE2,verilog,altera quartusII,7segmentled
led_0_7
- 与键盘扫描功能相对应,实现7段数码管的显示功能,在单片机中有较大用处。verilog-fullfill the function of displaying in verilog language. You can use it combined with keyboard scanning
Seg7decode
- verilog HDL的7段数码管译码代码,可以使用-7 segment LED decoder with verilog HDL
44keyboard-scan-in-FPGA
- Verilog语言的四乘四的键盘扫描程序。共阴共阳级数码管均能显示。-4 multiply 4 keyboard scan in FPGA