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seg7_deo1
- 七位数码管显示器，有源程序，编译仿真程序，verilog语言-7 digital tube displays, there is source code, compiled simulation program, verilog language
seg
- 用verilog语言实现数码管控制工作，有问题可以qq咨询，516998649-use the verilog language to drive the seg
baweishumaguan
- 利用Verilog hdl语言编写的8位数码管程序，这对于那些刚学Verilog hdl语言的学习者来说，是不错的入门程序，特别程序里头的分频程序模块，谢谢支持。-Using Verilog hdl language of the eight digital control procedures, which for those just learning Verilog hdl language learners, is a good entry procedures, especially
hdl
- ACTEL FPGA 6位数码管计数999999，Verilog描述-ACTEL FPGA 6 bits digital tube count 999999, Verilog descr iption
displayHELLO
- verilog语言编写，在altera公司的de2实验板上实现八个数码管循环显示HELLO-verilog language, in the experimental altera de2 board to achieve the company' s eight digital control loop shown HELLO
paobiao
- 用verilog 编写的数码管显示的秒表-Prepared using verilog digital display of stopwatch
sevenlight
- 自己编写的一些关于用verilog的七段数码管时钟显示-seven
xinjiaotong
- 自己编写的，使用Verilog语言辨析的在FPGA上实现的交通灯的红绿黄灯，用状态机实现，共有六种状态，红-绿、红-黄、左转弯、绿-红、黄-红、左转弯，每种状态配以数码管显示区分。-I have written, use the Verilog language Discrimination implemented in the FPGA, red, green and yellow traffic lights, a total of six states, red- green, red-
lcd
- 用Verilog写的数码管动态显示代码，可以直接使用，在quartus ii软件9.0以上版本运行-Verilog digital control with dynamic display of written code, can be used directly in the quartus ii software, version 9.0 or above to run
ex9
- 一个I2C通信协议的verilog代码，开发环境是Quartus 2,产生结果在数码管上显示-I2C communication protocol of a verilog code, development environment is Quartus 2, produce the results shown in the digital control
taxi
- 出租车自动计费器，使用verilog hdl语言编写，计费包括起步费、里程费、等待费，并利用八位数码管显示。-Automatic meter taxi, using verilog hdl language, including start charging fees, mileage fees, waiting costs, and use eight digital display.
adder2
- 此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器 、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器 、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例 ，特别是模为 60 的 BCD码加法计数器，这是我目前发现的最优源代码，应用于解码器领域。-This source code is based on the Verilog language def
paobiao
- 该程序是用verilog语言实现的数字跑表功能，其中分为计数模块与数码管显示模块。-The program is verilog language digital stopwatch function, which is divided into counting module with digital display module.
jianpan
- 基于FPGA的Verilog的控制PS2数字小键盘并在数码管显示相应的数字-Verilog FPGA based control of PS2 numeric keypad and digital display the corresponding number
seg
- verilog编写的时钟分频程序和数码管显示程序-verilog
miaobiao
- 秒表 数码管显示 采用verilog语言编写 Quartus II 9.0sp2 编译成功后生成的所有文件已包含-Digital display with stopwatch verilog language Quartus II 9.0sp2 successfully compiled all the files have been generated that contains
anjianshumaguan
- 按键与数码管显示 采用verilog语言编译 可在quarter ii编译 所有文件都包含了-Buttons and digital display with verilog language compiler can be compiled in the quarter ii files contain all
saomiao
- verilog源代码，实现四个数码管蛇形循环显示-verilog source code, snake-like loop realization of the four digital displays
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
LCD_KEY
- Verilog代码，由4*4扫描式键盘输入数字或运算符号，数码管上显示数字、同时LCD上显示数字或字符。-Verilog code scanning from 4* 4 keyboard input number or operator symbol, displayed on the digital numbers displayed on the LCD while numbers or characters.