搜索资源列表
statemachine11.2
- 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
FIR_1
- FIR滤波器的verilog实现，实现6级流水线的程序设计。-FIR filter Verilog, has implemented six lines of program design.
add_16_pipe
- 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
leg_source
- verilog hdl编写,六段流水线CPU.程序完整，功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
bbb
- AVS运动补偿电路的VLSI设计与实现 提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流 水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优 利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。
rgb2yuv
- verilog编写，rtl风格，流水线设计，实现图像rgb格式到yuv格式的转换。
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
CPU
- 实现了简单的CPU功能 采用三级流水线和超标量-CPU functions to achieve a simple three-stage pipeline and superscalar
mult_addtree
- 用VERILOG HDL 语言实现一个4位的流水线乘法器-VERILOG HDL language with a 4-bit pipelined multiplier
scoreboard
- MIPS体系结构用verilog实现的记分牌算法，标流水线-Architecture implemented using verilog scoreboard algorithm, standard line
pipe_mul8
- verilog实现的流水线8位乘法器，效率高，代码简洁经典-verilog implementation of pipelined 8-bit multiplier, efficient, simple and classic code
Fast-adder-design-using-verilog
- 用Verilog设计各种快速加法器（四位先行进位加法器、选择进位加法器、流水线加法器）-Verilog design all kinds of fast adder (four first adder, select adder pipelined adder)
8-grade-4-pipeline-adder-Verilog
- 这是一个8位4级流水线的加法器的Verilog程序。-This is a eight grade 4 pipeline adder the Verilog program.
DLX-pipeline-in-verilog
- verilog实现DLX指令集5段流水线-5 stage DLX pipeline implemented in verilog
flow_proc
- FPGA FLOW verilog流水线把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。以芯片面积换取时间，即面积换取频率-FPGA FLOW verilog To a complex pipeline logic is divided into several blocks to achieve a relatively simple, reduce the logic level signal, increasing the frequency. The chip a
BCH_VLSI
- 使用HLS完成BCH编码的运算通路的设计，纯组合逻辑，对于65nm工艺可跑上1GHz。已经组合逻辑分为了多个部分，可在每一个部分之间插流水线。 附上可综合的纯RTL Code以及C++代码，以及Modelsim仿真。 可通过我的优化选项来学习如何优化HLS工具生产的代码。(BCH Encoder realized using HLS tool. Combinational logic.)
CPU_Verilog
- 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
highperformance
- 最大公约数（GCD）stein算法实现，高性能流水线实现(The greatest common divisor (GCD) stein algorithm, high performance pipeline implementation.)
CPU-Pipeline
- 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
multiplier
- Booth乘法器是属于位操作乘法器，采用流水线结构实现(The Booth multiplier is a bit-operated multiplier that is implemented in a pipeline structure.)