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adc0809
- 1、用状态机设计A/D转换器ADC0809的采样控制电路，并在数码管上显示转换结果； 2、设置有复位和启动/保持开关，要求 ⑴ 复位开关用来使A/D转换器复位，并做好A/D转换准备； ⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果，即按一下启动/保持开关，启动A/D转换器开始转换，再按一下启/停开关，停止转换并保持结果。 3、采用Verilog HDL语言设计符合上述功能要求的控制电路。-1, with the state machine design A/
State-machine-design-techniques
- 状态机设计-英文-如何编写状态机-case-State machine design techniques for Verilog and VHDL
sencond_counter
- 在ise14.7开发环境下，用Verilog编写的秒表程序，其中通过状态机实现数码管的动态显示-In ise14.7 development environment, using Verilog prepared stopwatch program in which the state machine implementation through dynamic digital tube display
serial_number_check
- 序列检测，学习verilog三段式状态机的经典例程，modelsim仿真无误-Sequence Detection, three-state machine learning verilog classic routines, modelsim simulation is correct
Ch8
- 《Verilog HDL数字系统设计及仿真》第八章有限状态机的设计源代码-" Verilog HDL design and simulation of digital systems." Chapter VIII of the finite state machine design source code
lab9_2
- 用verilog实现更高级的交通灯：增加游行模式。实质上是对米粒状态机的掌握-An implementation in verilog on Mealy FSM
fsm
- 三段式状态机的典型写法，verilog实现-The three section type of typical state machine method, Verilog implementation
xvlijiance
- 附件包括四个内容1.采用Verilog编写的状态机实现序列检测的ISE工程2.代码文档一份3.原理说明4.使用说明。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Accessories include four content of 1 by the state machine Verilog prepared realize sequence detection ISE works 2 code document a 3 principle that 4 instructi
adc
- VERILOG编程，利用状态机实现对TLC549的采样控制，实验时可调节电位器RW1（在开发板底板左下角），改变ADC 的模拟量输入值，数据采集读取后在数码管上显示。 -Implementation of sampling control of TLC549 using state machine, adjustable potentiometer RW1 experiment (in the development board bottom left corner), change t
state-machine
- 一个简单的用verilog实现的售货机状态机设计，内有word介绍设计的原理-A simple realization of a vending machine with verilog state machine design, there are design principles introduced word
test-series-10010
- 用于检测序列10010的程序，Verilog的状态机练习-Used to test series 10010 program, Verilog state machine practice
autosell
- 自动售货机程序，以Verilog三段式描述方法描述有限状态机FSM，编译及输出正常-Vending machine program, describe the method described in Verilog three-finite state machine FSM, compile and output normal
tlc549adc
- 使用verilog编写的利用状态机实现对TLC549的采样控制，实验时可调节电位器，改变ADC 的模拟量输入值，数据采集读取后在数码管上显示。可以自己用万用表测一下输入电压， 然后与读取到的数据比较一下。-Use verilog prepared using the state machine to achieve the TLC549 sampling control, adjustable potentiometer experiment, change ADC The anal
fsm1
- 用verilog实现有限状态机，是摩尔型的，有详细代码-Finite state machines using verilog to achieve, is the molar type, a detailed Code
VHDL100
- 本文件包含100个Verilog实例，有存储器，时钟，椭圆滤波器，状态机等。有助于初学者的学习。-This document contains 100 examples of Verilog, there are memory, clock, elliptic filter, state machines. Help beginners to learn.
NandBuffer
- verilog编写，含三路正弦信号发生器，三路数据乒乓缓存模块。乒乓缓存读写控制采用三段式状态机实现。-The project contains a 3-channel sine generator and a 3-channel ping-pong buffer which is written in verilog. The write and read control of buffer is implemented in 3-segment FSM.
quartus
- 流水灯状态机的一段式描述和二段式描述还有三段式描述的Verilog源码-Light water section of the state machine and the two-stage type descr iption descr iption descr iption of Verilog source code as well as three-
fsm
- verilog语言，有限状态机实现的序列检测器-verilog language, finite state machine sequence detector
RISC_CPU
- 这是用verilog写的一个基于状态机的简易RISC_CPU的设计，里面包含各个模块，每个模块经过仿真没有问题，整个工程在板子上经过试验。-This is a verilog to write a simple RISC_CPU based state machine design, which contains various modules, each module through simulation without problems, the whole project tested o
AD7606
- AD7606的状态机驱动，并口模式，verilog代码，可正常使用。-AD7606 state machine drive, verilog code, can be normal use.