搜索资源列表
verilog_i10Mhz
- 10MHZ的频率的程序，验证过可以使用，有需要的可以下载(10MHZ frequency of the program, verify that you can use, there is a need to download)
verilog_i20Mhz
- 20MHZ的频率的程序，验证过可以使用，有需要的可以下载(20MHZ frequency of the program, verify that you can use, there is a need to download)
fredeng
- 用verilg语言实现等精度测量频率，最大可测100m。(Implementation of equal precision frequency measurement with verilg language)
frequency
- 基于Verilog HDL数字频率计的设计与实现(Design of Verilog HDL Digital Frequency Meter)
ex_DDS
- 基于Verilog语言实现DDS（数字频率合成器）的设计，有完整的工程设计代码和仿真脚本(Verilog language based on DDS (digital frequency synthesizer) design, there is a complete engineering design code and simulation scr ipts)
color_bar
- 使用verilog编写的模块，输出1080p彩条测试视频，输入时钟频率可以为74.25M或者148.5M(The use of Verilog module, 1080p color video output test, input clock frequency is 74.25M or 148.5M)
FPGA分频
- xilinx spant6 PLL分频，生成4个不同频率的时钟，实现LED闪烁。(xilinx spant6 PLL frequency division)
uart_ip
- 实现串口通信模块设置，包括频率分频、波特率产生、接口时序要求(Implementation of serial communication module settings, including frequency division, baud rate generation, interface timing requirements)
second
- 等精度测试，待测频率超过100就停止产生脉冲(Such as precision testing, more than 100 stopped produce pulse frequency under test)
fenpin
- 用verilog语言设计了一个分频器，晶振频率为50MHz(A frequency divider is designed in Verilog language. The frequency of crystal oscillator is 50MHz)
asd
- 频率计，自动计算输入频率并二进制输出显示。(cymometer; frequency meter)
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
signal
- 简易频谱仪 256位 采用了直接数字频率合成技术(DDS)和计算机控制技术，选择美国Analog Devices公司的高度集成DDS芯片AD9851和AT89S52单片机作为控制器件，设计了一种基于DDS的程控信号发生器。用C语言进行了软件应用设计。实验结果表明，该信号发生器能较好地产生较高稳定度的激励信号，具有较高的实用价值。(Simple spectrum meter 256 bit)
div_3
- 采用Verilog语言对时钟进行3分频，满足系统多时钟频率的要求(3 frequency division of clock in Verilog language to meet the requirement of multi clock frequency of the system)
fenpin4
- 使用fpga实现四分频，将单一频率信号的频率降低为原来的1/4。(Using FPGA to achieve four frequency division, the frequency of a single frequency signal is reduced to the original 1/4.)
pipelines
- 将组合逻辑系统地分割，并在各个部分之间插入寄存器，并暂存中间数据的方法。 将一个大操作分解成若干的小操作，每一步小操作的时间较小，所以能提高频率，各小操作能并行执行，所以能提高数据吞吐率。(A method to divide the combined logical system into a register and temporarily store the intermediate data between the parts. A large operation is decomp
CAR_LI2
- DE1-SOC实验开发板和Verilog HDL语言的交互式程序作品，选择避障小车作为课程设计题目，并根据选题制定了如下设计需求： 1.能实现基本的避障小车功能，即躲避障碍，变速，计分，计时显示游戏开始、进行和结束画面； 2.能实现人机交互功能，玩家可通过外接键盘或DE1-SOC开发板自带按键和开关操作小车转向； 3.能通过VGA在显示屏中显示，并且能达到5Hz的刷新频率； 4.能实现自定义小车和障碍物皮肤的功能；(DE1-SOC experiment development board
cymometer
- 使用XILINX公司出品FPGA开发板，基于verilog语言，实现简单的脉冲频率计功能；(The FPGA development board is produced by XILINX company, and a simple pulse frequency meter function is realized based on Verilog language.)
pinlvji
- 本文件用于测波形频率的verilog代码，是典型的数字频率计的源代码(This document is used to measure the frequency of the Verilog code, the source code of a typical digital frequency meter)
pwm
- 本程序可以实现输出不同占空比（0-100）和不同频率的pwm波形；满足驱动不同硬件的需求；(This program can output PWM waveforms with different duty cycles (0-100) and different frequencies, and meet the needs of different hardware drivers.)