搜索资源列表
EDA_project
- 基于Verilog和VHDL的DDS程序 基于VHDL的8位十进制频率计 -Verilog and VHDL based on the DDS process VHDL-based 8-bit decimal Cymometer
fb
- 占空比为1：1 的方波verilog程序，通过修改counter可以改变频率及占空比-1:1 duty cycle square wave of verilog procedures, counter can be changed by modifying the frequency and duty cycle
verilog2
- 本代码在Quartus II 9.0 (32-Bit)环境编译运行，使用SOPC_NIOSIIFPGA开发板，可作为入门级代码讲解，将50MHZ的频率改为1MHZ，并以此频率为基准计数显示在七段数码管上。（采用verilog语言）-The code in Quartus II 9.0 (32-Bit) environment to run the compiler, the use of SOPC_NIOSIIFPGA development board, entry-level code ca
dds
- 用VERILOG语言实现的dds(直接数字频率合成器)-VERILOG language with the dds (DDS)
fenpinqi
- verilog写的分频器，其最高频率为输入频率，没毛刺，挺好-written in verilog divider, the maximum frequency of input frequency, no glitches, very good
speaker
- verilog写的电子钢琴，内容简单，但频率与数字间关系的原理详尽，实验通过，供新手学习讨论-write verilog electronic piano, the contents of simple, but the relationship between frequency and number of the principle of detailed experimental passed, new learning
new_128HZ
- 直接数字频率合成器DDS设计，VERILOG实现的，比较好的哦-DDS direct digital frequency synthesizer design, VERILOG implementation, and better oh
complete
- 基于Verilog写的测信号频率和幅度得程序，可用-Written in Verilog-based test signal frequency and amplitude were procedures, can be used
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
verilog_16QAM
- 使用verilog实现全数字16QAM调制器，载波频率1MHZ，数据比特流的速率为100Kbps,-the modulation of 16QAM based on FPGA
DDS_Timing
- 数字频率合成器DDS，具有和单片机接口的直接数字频率合成器的FPGA实现代码（Verilog）-Digital Frequency Synthesizer
pinlvji
- 数字频率计的Verilog HDL语言实现，已经通过仿真-Digital frequency meter Verilog HDL language implementation has been through simulation
uart
- RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232
ondometer
- 用verilog语言编写的运行与FPGA上的基本的频率计程序，有各种数量级的精度，开发环境为quartus2-ondometer written by verilog
digital_frequency
- 用verilog实现数字频率计的设计，具有自动换挡功能，采用t法和m法设计，低频显示周期。量程为0.5~10Mhz。开发环境为quartus-This is a method of designing a digital frequency-measuring device. It can measure frequency ranging from 0.5Hz to 10MHz. It is developed in the program of Quartus.
xiangweileijiaqi
- 相位累加器，是数字频率合成器的重要组成部分。这是verilog代码。-Phase accumulator, digital frequency synthesizer is an important part. This is the verilog code.
Binarydivider
- 采用verilog编写的二进制分频器,常用于频率变化场合-Binary frequency divider using verilog prepared, commonly used in the frequency occasions
firfilter14
- 用Quartus II实现综合布线，要求充分利用Altera Stratix/Stratix II的器件的DSPBLOCK资源，Quartus II综合出的系统最高工作频率达到270Mhz以上.用Verilog进行编程。-Pipeline FIR structure。
div_k
- 此程序实现时钟的1/k分频，输入为一个复位信号rst_n,一个时钟信号clk，一个参数k；输出out为一个占空比为50 的时钟，频率为clk的1/k -this verilog programme divid the clock to 1/k in fluquency.
EDAplvj
- 4挡频率及设计 用于测量制定信号的频率 Verilog语言编写-4 block design used to measure the frequency and the frequency of the signal developed Verilog language