搜索资源列表
alu
- alu,利用verilog实现+、-、*、 、移位等功能-alu achieve+,-,*, , shift functions
alu
- 32位alu模块实现加减法、逻辑运算、移位、比较和置高位立即数等功能。verilog实现。-32-bit alu module achieves functions like addition and subtraction, logical operations, shift, compare, and set a high immediate number by verilog
alu
- verilog 编写的 可综合的ALU单元 可执行加减与或非 5种运算-verilog prepared by the ALU unit can be integrated with non-executable plus or minus five kinds of computing
ALU-and-Register-File
- ALU&Register Files(RF)之實現和其資料路徑的組合，包含了(1)ALU(2)Register File (RF)(3)Serial-in parallel-out register file(4)ALU + RF datapath-To learn the Verilog design for ALU and Register Files which are two main building blocks of a CPU.
ALU
- ALU，两种类型的verilog源代码，包括测试代码，原创。-ALU, two types of verilog source code, including test code, originality.
8-bit-ALU-with-a-Newton-Raphson-Divider
- 8-bit ALU with a Newton-Raphson Divider Using Verilog
alu
- verilog code for 8 bit alu
ALU
- Verilog编写的ALU，可实现数学、移位、逻辑运算-ALU Verilog prepared, enabling mathematics, shift, logical operations
alu
- My own arithmetic and logic unit in Verilog HDL.
alu
- 用Verilog HDL编写的简单算数逻辑单元-Algorithm Logic Unit programmed by Verilog HDl
ALU
- Verilog中的ALU设计，具备ALU的功能，十分详细。-The ALU Verilog design, with ALU functions, very detailed.
ALU
- This MIPS ALU verilog code-This is MIPS ALU verilog code
alu
- 用Verilog语言中的always块实现对输入数据执行加、减、与、或和求反的功能-Using Verilog language always realize the input data block to perform addition, subtraction, AND, OR, and negated function
ALU
- 算术逻辑单元,可以实现加法、减法、比较、移位、与门、或门等功能(arithmetic and logic unit)
CPU_Verilog
- 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
[Source code] 32bit_ALU_code_verilog
- 32bit ALU project source code
lab2
- 算数逻辑运算单元 使用verilog编写(Arithmetic logical arithmetic units are written in Verilog)
ALU_4bit
- 4-bit ALU in verilog
project_copy3
- 利用verilog实现的alu代码，可以进行加减移位等操作(Using Verilog to achieve Alu code, you can add, delete, shift and other operations)
各种基础module打包下载全集
- 例如分频器，alu，ram的verilog实现(The implementation of divider, alu, ram etc. in verilog)