搜索资源列表
exp3
- 指令设计实现及CPU控制器设计verilog实验报告，含源代码-The design and implementation of instruction and the CPU controller design verilog experimental report, including source code
pipeline_code
- 实现了MIPS五级流水CPU,用verilog语言实现-MIPS CPU verilog
cycle_code
- verilog实现了MIPS多周期（5周期）的CPU-verilog MIPS 5 cylce
pc-matrix
- 简单CPU verilog代码，完全按照COA中描述的结构，是微程序实现-simple structure cpu code, using verilog-HDL, totally struct the organization according to the COA,
8051
- 8051系列cpu用verilog编写的。-Verilog the compilation American standard encryption algorithm 8051 cpu hardware realizes contains the complete code and the test order.
8_RISC_CPU
- risc-cpu，简单的cpu设计,强大的功能简洁的设计，精简化-verilog risc_cpu
clk_gen.v
- 时钟发生器，用计数器功能编写的，能更好的潜入模块中,risc-cpu的一部分-clk_gen verilog
DataCycle
- 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-cpu cpu cpu cpu cpu cpu cpu cpu
PipelineSim
- 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
PIPELINE
- 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
PipelineCPU
- 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
Tomasulo2
- 用verilog编写流水CPU。采用Tomasulo算法，进一步的减少了等式右边的各项暂停时间，并通过阅读文献，实现了一种基于此算法原理的机器PowerPC 620的CPU的雏形-Tomasulo Based Speculative Processor
TVerriRiscCPPh
- 这个文件中使用verilog hdl简单易懂懂的运用基本运算实现了微型的cpu设计开发过程 -Verilog hdl straightforward to understand the use of basic operations miniature cpu design and development process used in this document
mips_single
- 這是以verilog所撰寫的MIPS single CPU文件檔。可完成簡單的加減運算。 -This is the verilog are written in MIPS single CPU document file. To be completed by the simple addition and subtraction.
MIPS_final-version
- 以Verilog所撰寫的Booth’s Algorithm Multiplier，可加到NiosII CPU之上，完成一道NiosII CPU的新指令。-Written by Verilog Booth,' s Algorithm Multiplier can be added to the above NiosII CPU to complete a the Nios II CPU command.
mp2
- 用verilog 写的微程序多周期CPU.软件版本为10.1-Micro-program written in verilog. Multi-cycle CPU software version 10.1
risc_cpu-OK
- 夏宇闻 verilog数字系统设计教程源码 第二版，实现了简单的RISC CPU。印刷版有误，已改正。- A simple RISC CPU Verilog HDL source code. Work well.
PipelineSim
- 用verilog编写的简单流水线CPU，指令集根据DLX指令集修改而来。只支持定点操作.-Verilog prepared by the simple lines with a CPU, instruction set modified from under the DLX instruction set. Supports only fixed-point operation.
LineEngine_tpf4
- Designing a Line Engine for CPU in verilog
BuildingPaPRISCPSystemPinPanPFPGA
- 一个32位 RISC CPU 核心，由Verilog 编写而成-A 32-bit RISC CPU core, written by Verilog