搜索资源列表
8086IP
- 开源CPU软核8086的源码,波兰版Verilog源码-8086 soft-core CPU revenue source, the Polish version of Verilog source code
mipsCPU
- MIPS CPU tested in Icarus Verilog
KD_CPU_src
- verilog语言写的8位CPU源代码，基本的算术运算和逻辑运算，对于学习计算机原理和verilog语言都有良好的效果-Verilog Language Writing 8-bit CPU source code, the basic arithmetic operations and logic operations, the study of computer principles and Verilog language has good results
Microprocessor
- 精通verilog HDL语言编程的一个不错的cpu 代码-Verilog HDL language proficiency of a good cpu code
111.ver
- verilog code for CPU design by Mohammad Hosseini.
CPU_verilog
- 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
8bit_RISC_CPU_RTL_Code
- 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
CPU
- verilog 实现的CPU，用Modelsim SE 6.2b 创建的工程，包含测试文件。- CPU of verilog implementation
cpu_16bit
- design cpu 16 bits by verilog HDL.
alu
- mcu，risc cpu Verilog源代码-mcu，risc cpu Verilog
mips
- MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
CPU
- Cpu with 8 bits in VHDL verilog Code
KD-CPU
- 计算机原理课程设计给予Verilog做的课题，丰富的指令支持，LOOP，TRAP、以及子程序调用等-Principles of curriculum design to do the computer issues a rich instruction support, LOOP, TRAP, and subroutine calls, etc.
CPU
- 实现了简单的CPU功能 采用三级流水线和超标量-CPU functions to achieve a simple three-stage pipeline and superscalar
cpu
- 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
cpu
- 用verilog实现的一个32位RISC处理器，能够实现简单的移位、加法等基本操作。-Verilog implementation with a 32-bit RISC processor to achieve a simple shift, addition and other basic operations.
CPU_Verilog
- 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
hamming
- verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)
CPU-master
- 单周期CPU的Verilog源码实现，基于Vivado(Single cycle CPU Verilog source code implementation, based on Vivado)
mips-cpu-master
- MIPS Implementation in Verilog. Full source code!