搜索资源列表
music
- 用FPGA实现的歌曲“梁祝”播放程序，用Verilog HDL编写-FPGA implementation with the song " Butterfly Lovers" player, written with Verilog HDL
232543
- FPGA Implementation of QFT based Controller for a Buck type DC-DC Power Converter and Comparison with Fractional and Integral Order PID Controllers
Realization_of_FPGA_for_LDPC_encoding
- 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror
PLL_50MHz_to_12MHz
- Verilog HDL语言编写EP2C8Q208芯片PLL分频的简单程序，50MHz分频为12MHz-Verilog HDL language，EP2C8Q208 chip， PLL frequency of simple procedures, 50MHz to 12MHz frequency
VGA_char_ROM_success
- Verilog HDL语言编写的基于M4K块配置ROM的字符数据存储VGA显示实验代码，引脚分配适用于21EDA的EP2C8Q208开发板, 详细解说请参见特权同学《深入浅出玩转FPGA》视频教程中的《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》-experimental code written in Verilog HDL language，ROM configuration based on M4K block for the cha
RTC
- actel fpga开发板fusion startkit实验例程，包含完整工程文件几verilog HDL 源码-actel fpga development board fusion startkit test routines, including the complete works of several verilog HDL source file
VGA
- 应用VEROLOG HDL编写的VGA的IP核，可用于SOPC BUILDER中-the control of the i2c bus
farrow
- 一份很好的数字时延程序（采用farrow算法），采用Verilog HDL，经过测试通过，是我一个雷达项目中的代替模拟时延的。精度很高，并有MATLAB程序验证-A good digital delay, Verilog HDL, procedures, is my test through a radar simulation project instead of the delay. Precision is high, and MATLAB validation
IS61WV51216BLL
- 备注：使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher M
XilinxFPGA(1-60)
- 系统地讲述了Xilinx FPGA的开发知识，包括FPGA开发简介，Verilog HDL语言基础、基于Xilinx芯片的HDL语言高级进阶、ISEd开发环境使用指南等-Systematically describes the development of Xilinx FPGA knowledge, including Introduction to FPGA development, Verilog HDL language based on chip-based Xilinx HDL La
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
verilog-study
- VERILOG HDL的入门学习资料，对于想进一步学习FPGA的朋友有一定的帮助。-VERILOG HDL entry-learning materials, for those who want to learn more FPGA' s friends have some help.
UART
- Verilog HDL写的实现ＵＡＲＴ收发程序-Realization of Verilog HDL UART receive written procedures
FPGA-Introduction
- 简单介绍Verilog HDL语言和仿真工具，主要应用领域，了解Verilog 的发展历史 -Brief introduction to Verilog HDL language and simulation tools, the main application areas to understand the historical development of Verilog
synth_fft
- fftprocessing can complete 256 pointsFFT.-Hardware Descr iption Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools
Verilog-HDL-jiaocheng
- verilog 教程，里边有很多个verilog学习方面的教程，有开发板自带的一些，还有些是本人自己收集整理的，很实用，也适合FPGA爱好者，很不错。-verilog tutorials inside many a verilog tutorial learning, development board comes with some, and some is my own collated, it is practical, but also for FPGA enthusiasts, ver
design-of-CAN-based-on-VHDL
- 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the C
FPGA-verilog-fenpin
- FPGA最常用的功能，分频，利用verilog HDL语言实现的，非常适合初学者。-FPGA most commonly used functions, frequency, using verilog HDL language, and is ideal for beginners.
div_frequency
- 任意分频器，用Verilog HDL实现，只需修改参数可以实现奇数、偶数分频，FPGA应用必备资料。-Any divider, using Verilog HDL to achieve, simply modify the parameters can be achieved odd, even frequency, FPGA applications necessary information.
jing-dain--FPGA-cheng-xu
- 关于FPGA的经典算法，包括数码管的编程和显示，用Verilog HDL语言写的程序，在开发板上已经测试成功！-Classical algorithm on the FPGA, including digital programming and display, using Verilog HDL language to write programs, the development board has been tested successfully!