搜索资源列表
FPGA_Project_Files
- 基于sdram的pci设计，包含整个工程，verilog编写-The design is base on sdram, contain a whole project ,using the verilog language.
Verilog_module
- micron 1G内存条verilog模型，对应具体信号为MT8HTF12864HZ-800，内存颗粒为MT47H128M8CF-25-micron 1G DDR2 SDRAM verilog module
tut_DE2_sdram_verilog
- DE2 sdram 的verilog 教学材料-tut_DE2 sdram verilog.
memory-controller
- 存储控制器，包括CPUside，接口，MEMORY side三个部分，使用verilog语言-This represents the "memory controller" It runs with the assumption that it is being connected to PC100 SDRAM.
FSM
- FPGA学习资料，新手入门资料,VERILOG- Micron SDRAM DDR2 Simulation model Verilog
altera_sdram
- 基于quartus平台的sdram控制器设计（verilog 源码）-Based on the the quartus platform, the SDRAM controller design (Verilog source code)
Sdram_Control_4Port
- 使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上-Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII
Design-Of-DDR-SDRAM-Using-Verilog-HDL
- implementation of ddrsdram
sdram_mdl
- SDRAM的FPGA 工程。用Verilog编写。器件型号为K4S641632，经过实验板验证，绝对可用。-SDRAM FPGA project. Written in Verilog. Device model K4S641632, after the experimental board, absolutely available.
SDRAM_verilog-serial-port
- FPGA对sdramd的操作，verilog语言设计！-FPGA SDRAM verilog
sdram_mdl
- FPGA控制SDRAM的工程，是用Verilog写的，很好用-FPGA to control the SDRAM project is written in Verilog, easy to use
SDRAM_verilog
- 关于FPGA控制SDRAM笔记详细的资料，verilog写的程序，注释也很详细，值得参考。-FPGA control SDRAM notes detailed information, the program written in Verilog, comments are also detailed, it is also useful.
sdram_me
- 用verilog代码控制sdram,sdram_module是顶层模块。控制8M x 16bits x4Banks sdram. -use verilog program to control the sdram
sdram_mdl
- SDRAM的verilog程序控制模块，希望对大家有帮助-SDRAM verilog program control module, we want to help
SD_SDRAM_LCM_PROJECT
- verilog控制SD卡与SDRAM之间数据传输及LCM显示，希望对大家有帮助-The verilog Control SD card with SDRAM between data transmission and LCM hope everyone
eetop.cn_SDRAM
- 实现sdram控制器的verilog代码，很好的学习资料-The sdram controller verilog code, very good learning materials
DE2_70_NIOS_10_flash
- 首先将此Verilog程序下载到DE2-70开发板上后，然后用NiosII软件将任何文件的二进制数据写入到ssram或者sdram等存储器重去，并可以指定起始地址。-First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdra
LL
- verilog语言描述的SDRAM程序代码。-verilog language to describe the the SDRAM procedure code.
sdr_ctrl
- SDRAM控制器源码 Verilog描述-SDRAM controller Verilog source descr iption
lpddr_verilog_model
- 美光 ddr sdram 仿真模型， 不可综合，用在测试平台模仿ddr sdram的功能。verilog语言编写。-Micron MOBILE DDR SDRAM simulation model. not synthesisable, used in tesetbench to emulation the function of ddr sdram. written in verilog