搜索资源列表
sram_fifo_uart
- 用verilog HDL编写的SRAM+FIFO+UART模块,欢迎各位指点 -Welcome to the guidance written in verilog HDL SRAM+FIFO+UART module
uart16
- verilog hdl语言,16位串口收发程序,波特率96-verilog hdl uart 16 9600
or1200_sopc
- 用verilog语言编写的or1200+wishbone总线+串口uart+片上ram,最小系统soc。包括片上ram的软件系统(C语言编写)都有。但下载者要使用此系统需要很多工具链,搞soc的应该都装好了。 绝对原创!用quartusII11.0在Altera DE2-115上验证通过,Modelsim SE 6.5f仿真通过。-It s very strange for Chinese people communicating with each other in English. Ri
RS-232CUART
- 主要是利用FPGA进行串口的通信 其中利用到FPGA的开发软件QUARTUS -verilog NIOS UART
FPGA_uart
- fpga实现串口通信 verilog语言实现 -uart communication using FPGA Verilog language implementation
V0p10
- 完整的基于verilog HDL语言UART代码~-Complete based verilog HDL language UART code to
uartverilog
- 基于fpga的verilog写的uart串口通信实验-Based fpga the verilog write uart serial communication experiment
UART_TXD_RXD_Verilog
- 开发异步串口FPGA逻辑的说明文档及代码,其中代码用Verilog编写,我就是看这些文档和源码编写了自己的串口程序-uart,txd,rxd ,select baud
uart_tx_and_rx
- A verilog code for UART transmitter and receiver system-A verilog code for UART transmitter and receiver system...
fifo_uart
- uart的verilog代码,包含fifo,并且采用过采样以防止噪声的干扰-uart verilog code
code
- 是用verilog写的带uart的简单controller,使用的是mips指令,用modelsim仿真,波形正确-With uart verilog write a simple controller, use the mips instruction the modelsim simulation, waveform correctly
uart1
- this is uart based verilog code for all the beginners
UART_verilog
- UART串口verilog代码-The UART serial verilog code ..........
UART_Transmitter_Arch
- 自己编写的带有FIFO的UART串口发送模块,代码通过状态机实现,开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog
uart_rtl
- uart模块的rtl代码,verilog编写。-uart module rtl code, verilog prepared.
uart_tx_rx_baudselct
- 使用verilog语言设计的一个uart的源码,可以进行波特率选择。-A uart source code using Verilog language design, baud rate selection.
UART_TX
- UART收发,verilog语言,测试成功-UART transceiver, verilog language, the test is successful
iic_com
- 用verilog语言实现IIC读写与并通过UART协议在串口PC显示,实现数据收发-IIC using verilog language and literacy with the PC via the serial port UART protocol display, data transceiver
mmuart_latest.tar
- uuart 串口的verilog 源码实现,欢迎下载使用. uart 串口 verilog-uuart serial verilog source implementation, welcome to download
UART_FPGA_Code
- UART FPGA实现过程文档说明,及VERILOG HDL 代码,希望能帮助有需要的人,-UART FPGA implementation process documentation, and VERILOG HDL code, hoping to help people in need, thank you