搜索资源列表
div
- 32位整数阵列除法器，verilog代码编写，性能高效。-32-bit integer array divider, verilog coding, performance and efficient.
PLL_12MHz
- 用verilog语言制作一个PLL，这个PLL可以将频率除频到12MHZ，将PLL除频成12MHZ输出-Verilog language production with a PLL, the PLL frequency divider can be to 12MHZ, 12MHZ into the PLL output divider
streamline_divider
- streamline 除法器，是国外一个工程师所写,verilog语言，modelsim测试-streamline divider
fangbo
- 一个可切换分频的时钟分频器的verilog语言，可根据具体情况修改参数实现不同的分频-A switchable clock divider divider verilog language, modify the parameters according to the specific circumstances of different sub-frequency
verilogdiv_3_5_7
- verilog写的奇数分频，适合初学的同学分析，容易上手，已测试。-verilog to write the odd divider, suitable for beginner students, easy to use, have been tested.
gray
- verilog语言编写的十分频器源码和测试文件-a program of ten divider,with a source and test file,using the verilog language
clock
- 利用verilog语言在fpga上实现不同分频器的设计，适合初学者学习-Verilog language in different divider on the fpga design, suitable for beginners to learn
div
- restoring divider in verilog
Clk_5
- 本文件为verilog所描述的基数分频技术，此实例为5分频电路。-This file is the verilog described base sub-band technology, this instance as a divider circuit.
verilog-HDL-Divider
- 两个3位二进制数的除法，结果（整数商）输出到数码管显示-Division, the result (integer quotient of two 3-bit binary number) output to the digital display
Verilog_div_frequency
- 本文使用实例描述了在 FPGA/CPLD 上使用 Verilog进行分频器设计，主要包括50 占空比的奇数分频. -This article uses the example describes the crossover design using Verilog in FPGA/CPLD, including the 50 duty cycle odd divider
modeldiv5
- 无分频电路，实现电路的五分频verilog代码，通过modelsim的仿真-No divider circuit circuit fifth frequency verilog code through modelsim simulation
led
- verilog编写的分频计数器，控制xilinx板子上led灯-verilog written divider counter control xilinx board led lights
Div
- 非常好用的小数除法器，verilog开发的。quartusii下综合通过-Very easy to use fractional divider, verilog developed. quartusii under comprehensive by
verilog_example
- verilog实例，多路器，除法器，数字跑表的多种实现方法-verilog example, the multiplexer, a divider, a digital stopwatch many implementations
cshiyan2012
- 基于EDA软件平台上，用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器，基于选项法中频调制器，再将各个模块综合起来组成一个完整系统；并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware descr iption language verilog design complete shift of the frequency divider,
clkdiv
- 任意分频电路的verilog实现，包含奇分频和偶分频-Arbitrary divider circuit verilog achieve, contains odd and even frequency divider
pll
- 用verilog实现奇数分频器程序，通过仿真验证-Odd divider program is verified by simulation with verilog
verilocode1
- verilog code1 of 32bit divider is uploaded
div_any
- 任意整数N分频器的verilog代码，N需要代码中进行设置-Any integer N divider verilog code N need to code set