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240_Report
- IMPLEMENTATION OF MEMORY TRANSFER in VERILOG.
fir_memory
- 用memory编写的verilog代码，可用于工程应用，已经过仿真-Verilog code written with the memory can be used for engineering applications, has been simulation
ntc
- NTC电阻在VERILOG HDL中的曲线表，使用1MA恒流源供电，用AD对其采集电压，并以12BIT形式输出查表即可达到实际温度值，本表占用450个12位存储单元-NTC resistor VERILOG HDL in the curve of the table, use the 1MA current source power supply voltages were collected with AD and in the form of the output look-up table
memery
- 通用存储器用Verilog hdl的实现，这是一个比较常用的源码，文档中有很详细的注释，初学者应该可以看懂。-Universal realization of the memory with Verilog hdl, this is a common source, the document very detailed notes, beginners should be able to understand.
DirectX_Updater
- Do I HAVE to backannotate to use these models? No but, to ensure correct results, you must pass the correct values to the models s generics. This can be done by editing the model s instantiations in your netlist. SDF backannotation may be easier
SDRAM
- 基于SDRAM的存储器接口设计，采用verilog编写-SDRAM memory interface design based on
MIPS1CYCLE
- MIPS single-cycle processor design in verilog.Instruction memory to the design and initialise it with your assembly code-a. Load the data stored in the X and Y locations of the data memory into the X and Y registers. b. Add the X and Y registers an
FIFO
- FIFO的VERILOG代码编写 可综合的Verilog FIFO存储器-The VERILOG code FIFO write comprehensive Verilog FIFO memory
HighSpeedFIFOsInSpartan-IIFPGAs
- This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be chan
mem
- verilog硬件描述语言开发的memory-verilog hardware descr iption language developed memory
mem_test
- ROM存储器的Verilog测试程序，希望对大家有帮助！-ROM memory of the Verilog test program, we want to help!
project1_supplemental1
- these are projects based on verilog like memory control, sdram control etc-these are projects based on verilog like memory control, sdram control etc..
modelsim-examples
- 这两个examples 的源码是modelsim 自带教程里面最重要的两个！但是其中一个（memory）在大多是安装文件目录下没有，但是又很有用，我找了好久才找到,PDF上说这几个文件在：<modelsim安装目录>\examples\memory\verilog下:dp_syn_ram.v,ram_tb.v,sp_syn_ram.v 但是找过的人都知道，一般的版本下面都没有这个源码。我分享一下，方便大家查找！-These two examples of the source is
ece5742010hw9CPU
- 用verilog语言实现CPU， 其中包括几个不同的模块，每个模块中间由总线进行连接-implement the CPU using Verilog language, including the memory, controller,data path, the logic unit.
memc_with_fifo
- Verilog编写的Memory Controller代码，用于AMBA总线下-Verilog code written in Memory Controller
mysram
- 静态存储器设计 VERILOG HDL描述-VERILOG descr iption of the static memory
FIFO
- verilog 实现FIFO存储功能，八位数据宽度，16数据深度。-verilog achieve FIFO memory functions, eight-bit data width, the depth of 16 data.
simple_CPU
- 通过利用verilog语言编写一个简单的处理器，并添加存储器功能-Verilog language through the use of a simple processor, and add the memory function
InstMemory
- instruction memory code in verilog for pipeline processor
Verilog_Rom
- the read only memory can design using the verilog in a HDL language.