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FIFO2
- 用verilog HDL语言编写的fifo存储器源文件 -Using Verilog language HDL FIFO memory source file
DDS-frequency-synthesizer
- 本文主要讨论了Verilog语言的基于DDS的波形发生器的设计。从设计要求入手，本文给出了DDS的详细设计过程，包括各个模块的设计思想，电路图，Verilog语言程序代码。其大致思想为通过频率控制字和相位控制字去控制正弦函数的ROM存储表的地址并对应着得到其幅度值，最终达到输出需要波形的目的。-This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Star
RSN
- “Randomized Smoothing Networks” introduced the idea of using networks composed of a type of comparator/memory element, initialized to random initial states, to create smoothing networks, which take arbitrary input loads into the network and produce a
VGA_CCD531
- 本文围绕一个包含Nios II软核处理器的可编程片上系统展开数码相机的样机设计。论文首先对样机所要达到的整体功能进行了规划，接下来并行开展了软硬件设计。在硬件方面，充分利用了所使用平台提供的SD卡插槽、键盘、数码管、SRAM等各种硬件资源，并用Verilog HDL硬件描述语言设计了样机系统所需要的VGA接口控制器、CMOS图像传感器接口控制器以及VGA显示存储器；在软件方面，本文基于Nios II软核处理器用C语言实现了SD卡的驱动、FAT文件系统的移植、VGA显视器的驱动以及BMP图片文件的
am29bdd160g
- 16 Megabit (1 M x 16-bit/512 K x 32-Bit), amd 公司 2.5 V电压, flash存储器仿真读写verilog 模型。-16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory verilog model.
DE2_70_NIOS_10_flash
- 首先将此Verilog程序下载到DE2-70开发板上后，然后用NiosII软件将任何文件的二进制数据写入到ssram或者sdram等存储器重去，并可以指定起始地址。-First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdra
Memory_tpf4
- Designing a memory in verilog
AXI_MIG
- ISE生成的AXI接口的MIG，内存控制器，语言：verilog-ISE generated the AXI interface MIG, memory controller, language: verilog
lab-2-Memery-design-with-VerilogHDL
- 用verilog 编写的32位存储器代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-32-bit memory code written in verilog, through modusim simulation, including the principle diagram and code, in the form of a lab report write
IIC_EEPROM
- 这是FPGA用Verilog写的IIC协议，可以对存储器进行简单的读取。-This is the FPGA using Verilog IIC protocol, you can perform simple memory read.
LCD12864fanye
- 12864显示驱动程序，支持翻页显示，功能类似电子书，支持存储器，Verilog语言。-12864 display driver support page display, similar to e-book function, support for memory, Verilog language.
basic-cache
- Verilog codes for cache memory with direct mapping and write back policy.
labfiles.tar
- A direct mapping cache memory with write back policy written in verilog.
NandFlash
- NandFlash Controller: It s contain a NandFlash controller in verilog language. It is a interface between microprocess and NandFlash memory.
usb
- USB slave: It is contain a USB slave design written in verilog language. It is a interface between USB host and Functions such as memory, Keyboard, mouse and so on.-SB slave: It is contain a USB slave design written in verilog language. It is a inter
ssram_latest.tar
- SSRAM接口,就是同步静态随机存取存储器接口整个工程文件，包括从前端verilog设计到后端仿真的整个工程-SSRAM interface is synchronous static random access memory interface entire project, including the design from the front to the back verilog simulation of the entire project
MRAM2012
- STT-MRAM磁性存储器全部verilog代码和仿真验证代码，包括行为模块，读写模块和控制模块，已经经过验证完全正确-STT-MRAM magnetic memory all the code and simulation code, including behavior module, reader module and the control module, has been proven entirely correct
Quartus
- VERILOG AD采集程序 FIFO存储-VERILOG AD acquisition program FIFO memory
cam
- CONTENT ADDRESSABLE MEMORY IN VERILOG
SPI-flash
- ST公司的M25Pxx SPI flash memory的verilog仿真模型，该模型准确地描述了SPI flash memory的行为，包括读，写，擦除等操作，可以用来挂在带有SPI接口的soc外部，方便验证SPI接口。 -ST' s verilog simulation model M25Pxx SPI flash memory, the model accurately describes the SPI flash memory behavior, including readi