搜索资源列表
pipeline_mipscpu
- 运用Verilog语言实现MIPS五级CPU的功能，能下载实现-5-level MIPS CPU based on Verilog
multi_cpu
- 用verilog语言编写的简单多周期CPU代码，在Sparten3板上可运行。实现了加、减、与、或、非等MIPS指令。-Verilog language with a simple multi-cycle CPU code can be run in Sparten3 board. Realization of add, subtract, and, or, not, etc. MIPS instruction.
cpu_design
- FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
mips_file
- mips files uploaded full verilog sourse code
Project-8
- 课程设计时用verilogHDL写的MIPS CPU-MIPS CPU coded with Verilog HDL
Elham-Zahraei-Salehi_-Sina-Saharkhiz-(1)
- here it is a file which is consist of design of a MIPS pipeline in verilog, it also has test part an it work perfectly. the code is written in good way to understand it easily
CPU
- 使用Verilog HDL语言完成一个简单的多周期MIPS微处理器的设计-Using Verilog HDL language to complete a simple multi-cycle MIPS microprocessor design
COA_PRO
- 简单MIPS流水线指令集的verilog实现。初步实现了branch 的功能。-implement of Pipelined MIPS processor
MIPSCPUverilog
- mips流水线CPU的实现，用的是verilog语言，描述了整个cpu的过程。存储、指令、处理等。-mips CPU Verilog
mips_pipelined2
- verilog code for mips
ppv2
- pipeline流水线用MIPS实现，用的是verilog。解决流水线的各种冲突。-pipeline pipeline with MIPS implementation, using verilog. Resolve conflicts pipeline.
openmips
- 一个开源mips处理器verilog 源码-wishbone interface wishbone interface
ALU
- This MIPS ALU verilog code-This is MIPS ALU verilog code
project_1
- 使用fpga实现mips处理器代码verilog-Use Code verilog fpga realize mips processor
sc_computer_2
- Verilog单周期CPU实现,可以实现简单的mips指令，附Verilog源码-Verilog achieve single-cycle CPU
m_cycle_mips
- verilog设计的5状态多周期mips -multiple cycle mips CPU design of Verilog
Implement-a-CPU
- 在FPGA赛灵思基础3上使用Verilog HDL实现支持MIPS操作子集的CPU-Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3
PipelineCPU
- 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU，含代码工程文件和相关设计说明文档，比较详细。-verilog HDL, 32 MIPS pipeline CPU
single_period
- 实现了单周期的数据通路，已通过基础的指令测试。(This program has finished single period .)
soc_sram_func
- 利用verilog编写的32位 MIPS指令集CPU，sram接口，已上板验证(The 32 bit MIPS instruction set CPU, SRAM interface written by Verilog has been verified on board.)