搜索资源列表
mt48lc32m16a2
- SDRAM的仿真模型Verilog。用于美光mt48lc32m16a2,可在ModelSim下用。-Simulation Model of SDRAM
pud_ben
- Verilog HDL source code of generating a ROM file (in Quartuss) and testbench in Modelsim (verification)
dvi_demo
- DVI demo用Verilog编写,有modelsim的测试-DVI demo write by Verilog-HDL,test by modelsim.
sinewave-case
- 利用verilog语言以及case语句实现正弦波波形,并利用modelsim完成波形仿真。-Use verilog language and case statement to achieve sinusoidal waveform, and use modelsim complete waveform simulation.
test_uart
- verilog 编写的串口发送和接收模块,能够设定停止位和校验位,并且包含了modelsim仿真文件。-verilog prepared by the serial port to send and receive module, capable of setting the stop bit and the parity bit, and includes modelsim simulation files.
Triangle
- 在ISE环境下,使用Verilog语言,编写三角波程序,运用ModelSim进行仿真。-In the ISE environment, use Verilog language, written in a triangular wave program, using ModelSim simulation.
New-Compressed-(zipped)-Folder-(5)
- traffic light controller verilog code modelsim tested
cal_pipeline
- 用system verilog 来实习的 1 stage pipeline calculator. It has been successful compiled in Modelsim-System Verilog Calculator
FIFO1
- 给出一个位宽16比特,深度为10的异步FIFO的设计,并要求给出空或满的指示信号。要求用Verilog HDL语言设计,并编写测试激励,以及用Modelsim进行功能仿真,验证设计正确性。10个16位的数据 (FIFO的宽度:也就是英文资料里常看到的THE WIDTH,它指的是FIFO一次读写操作的数据位,就像MCU有8位和16位,ARM 32位等等。FIFO的深度:THE DEEPTH,它指的是FIFO可以存储多少个N位的数据(如果宽度为N)。如一个8位的FIFO,若深度为8,它可以
VendingMac
- Verilog实现的自动售货机,使用有限状态机进行处理。包括Modelsim和Spnplify的综合工程。-Verilog realize vending machines, using a finite state machine for processing. Including integrated engineering and Spnplify of Modelsim.
jtdverilog
- 交通灯,verilog,VHDL,modelsim-Traffic lights, verilog, VHDL, modelsim ,,,,,,,,,,
cpu_me
- 采用verilog编写的cpu,modelsim仿真均实现8条指令功能,有虚拟ram和rom-Using verilog prepared cpu, modelsim simulation functions are to achieve eight instructions, there are virtual ram and rom
fft1024-verilogCODE
- fft 1024点verilog代码,适用于基-4的FFT算法描述,使用quartus,modelsim,-fftpoint 1024 verilog code
iic
- 通过verilog语言实现了关于IIC协议,并且通过了modelsim的功能仿真验证以及板卡之间的RTL调试。-the verilog code about IIC standard,checked by modelsim,and make ture the IIC function in RTL。
DCT
- 用Verilog HDL编写的离散余弦变换,可用于视频图像压缩,并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
Dijkstra
- 用verilog 实现求最短路的Dijkstra算法,用modelsim仿真通过,数据真确,-Dijkstra implemention with verilog base on FPGA
key_filter
- 用于FPGA的按键消抖的Verilog文件,经过modelsim仿真和下板验证。-Verilog file for FPGA key debounce, after modelsim simulation and verification under the plate.
my_i2c
- 基于FPGA的i2c通信,使用Verilog hdl实现,带有功能说明文档、ise工程、modelsim仿真工程-i2c communication based FPGA using Verilog hdl implementation, with the function documentation, ise project, modelsim simulation project
UART
- 用Verilog实现uart串口通信,并在Quartus和modelsim上完成测试和仿真,内含源代码和测试程序。-Using Verilog realize uart serial communication, and complete testing and simulation in Quartus and modelsim, including source code and test procedures.
SRAM
- 用Verilog实现8051sdam,并在Quartus和modelsim上完成测试和仿真,内含源代码和测试程序。-Using Verilog realize 8051sdam, and complete testing and simulation, including source code and test procedures in Quartus and modelsim.