搜索资源列表
statemachine11.2
- 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
5_lined_cpu
- 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
cordic
- vhdl语言编写的cordic算法，实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
CPU
- 实现了简单的CPU功能 采用三级流水线和超标量-CPU functions to achieve a simple three-stage pipeline and superscalar
PIPELINE
- 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
pipeline
- 以Verilog撰寫而成的Booth’s Algorithm Multiplier，並以Pipeline方式實現。-Written in the Verilog Booth' s Algorithm Multiplier, and the Pipeline way.
Pipeline-2.zip
- Pipeline processor verilog components ,Pipeline processor verilog components
Pipeline-3.zip
- Verilog codes for pipelined processor,Verilog codes for pipelined processor
8-grade-4-pipeline-adder-Verilog
- 这是一个8位4级流水线的加法器的Verilog程序。-This is a eight grade 4 pipeline adder the Verilog program.
pipeline
- 一个流水线设计提高FPGA运行主频的实例-a pipeline demo for FPGA written with verilog
DLX-pipeline-in-verilog
- verilog实现DLX指令集5段流水线-5 stage DLX pipeline implemented in verilog
8-point-pipeline-fft-by-verilog.pdf
- 简单的8位基2 流水 fft verilog-Simple 8 base 2 pipelined fft verilog
pipeline
- 使用VERILOG實現MIPS2000的PIPELINE-Use VERILOG realized MIPS2000 the PIPELINE
pipeline
- 简单的流水线的实现机制，基于verilog语言。-The pipelined implementation, based on Verilog language.
Cordic-arithmetic-pipeline
- FPGA实现基于Cordic算法的流水线结构设计，相关verilog语言代码-FPGA to realize the Cordic code
CPU_Verilog
- 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
highperformance
- 最大公约数（GCD）stein算法实现，高性能流水线实现(The greatest common divisor (GCD) stein algorithm, high performance pipeline implementation.)
pipelines
- 将组合逻辑系统地分割，并在各个部分之间插入寄存器，并暂存中间数据的方法。 将一个大操作分解成若干的小操作，每一步小操作的时间较小，所以能提高频率，各小操作能并行执行，所以能提高数据吞吐率。(A method to divide the combined logical system into a register and temporarily store the intermediate data between the parts. A large operation is decomp
multiplier
- Booth乘法器是属于位操作乘法器，采用流水线结构实现(The Booth multiplier is a bit-operated multiplier that is implemented in a pipeline structure.)