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ppv2
- pipeline流水线用MIPS实现，用的是verilog。解决流水线的各种冲突。-pipeline pipeline with MIPS implementation, using verilog. Resolve conflicts pipeline.
0340196Lab3
- 这是用Verilog语言编写的带有pipeline功能的CPU，适合于学习计算机组织的同学-This is a Verilog language functions CPU with pipeline for students to learn computer organization
cal_pipeline
- 用system verilog 来实习的 1 stage pipeline calculator. It has been successful compiled in Modelsim-System Verilog Calculator
liushui
- 本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写-This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
mips
- 基于mips架构的五级流水线硬件实现。使用verilog-Based on the five-stage pipeline hardware architecture mips
pipeline_add
- pipeline式累加器的verilog代码和testbench文件，已验证-pipeline type accumulator verilog testbench code and documents, verified
pcpu_handle_mem
- Verilog实现五级流水线CPU，hazard以及时序功能已经实现。-Realize five-stage pipeline CPU
PipelineCPU
- 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU，含代码工程文件和相关设计说明文档，比较详细。-verilog HDL, 32 MIPS pipeline CPU