搜索资源列表
counter8
- 8 位 计数器，带使能键和重置键。附带testbench, verilog 环境-8 bit counter
traffic_tb
- verilog， 铁路道口异步交通灯设计的testbench.-testbench for an asynchronous circuit that is to control the gates and red flashing light at a railway level crossing,
code
- 用Verilog写的采用LSM算法的自适应性FIR滤波器，有testbench和主体代码，亲测可用-Written using Verilog LSM algorithm using adaptive FIR filters, and the body has testbench code, pro-test available
mem
- 一种用于测试SRAM阵列的MARCH-C算法；使用Verilog语言描述，包括SRAM模块、MRACH-C算法还有testbench-An algorithm for MARCH-C test SRAM array using Verilog language descr iption, including SRAM module, MRACH-C algorithms as well as testbench
spdif_verilog
- 数字音频接口spdif ip core，verilog语言编写，带有testbench-spdif verilog ip core
lab1
- 初步掌握ModelSim的使用方法,了解TestBench的编写,Verilog HDL的层次设计方法/参数设置、参数传递方法.-Preliminary master the use of ModelSim understand TestBench preparation, Verilog HDL level design methods/parameters, parameter passing methods.
AES
- AES加解密Verilog HDL源代码，具体的算法参照相关书籍，里面含有testbench-AES encryption and decryption Verilog HDL source code, reference books specific algorithm, which contains testbench
CA-code
- 生成CA码verilog代码，quartusII开放环境，含源代码和仿真文件（波形、testbench）-CA generated code verilog code, quartusII open environment, including source code and simulation files (Waveform, testbench)
Sawtooth_Wave
- verilog写的锯齿波程序，基于DDS原路的。内含testbench仿真文件。功能十分强大-verilog write sawtooth program, based on the same route of DDS. Embedded testbench simulation files. Is very powerful
fifo_verilog
- 16位FIFO的硬件电路，使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现，以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
halfadder.v.tar
- Verilog Code for Half Adder Circuit with testbench code-Verilog Code for Half Adder Circuit with testbench code...
fulladder.tar
- Verilog Code for Full Adder circuit with Testbench file-Verilog Code for Full Adder circuit with Testbench file...
basicgates
- Verilog Code for Basic Gates implementation with testbench-Verilog Code for Basic Gates implementation with testbench..
mux4_1
- Verilog Code for 4*1 Multiplexer with testbench file-Verilog Code for 4*1 Multiplexer with testbench file...
8bit_decoder
- Verilog code for 3*8 Decoder Circuit with testbench file-Verilog code for 3*8 Decoder Circuit with testbench file....
Haffman-encoding
- verilog implementation of huffman encoder with testbench
xor2
- 基于VERILOG的异或实现和其testbench-XOR-based realization and its testbench VERILOG
32bit_multiply
- 包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。-Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementat
testbench_verilog
- Verilog语言中的testbench的语法教程，可供参考，分享分享-Verilog language in the testbench grammar, reference, share
CAN
- 包含CAN协议讲解与CAN协议控制器的verilog实现(含有testbench），该实现模仿SJA1000架构，接口完全一致。压缩包中还包含SJA1000的手册与应用指南，非常好的CAN学习资料。-CAN protocol controller implemented in Verilog（contain testbench） & instruction of CAN protocol & datasheet and user manual of SJA1000