搜索资源列表
how-to-write-testbench
- 如何写好testbench,针对verilog语言-how to write testbench，aimed to verilog
testbench
- VHDL和verilog的TESTBENCH 编写方法。非常好的资料。英文的,但很简单。-Written in VHDL-TESTBENCH. Very good information. In English, but very simple.
A-Verilog-HDL-Test-Bench-Primer
- 学习资料：详细说明了如何用Verilog语言编写Testbench文件-Learning materials: detailed descr iption of how to use Verilog language Testbench file
labs_system_verilog_testbench
- system verilog testbench 对应代码。-labs for system verilog testbench
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route
Testbench
- 这是一段verilog的调用测试例子，可以以此作为参考，对其他verilog仿真时，进行调用。-This is a verilog call the test example, can be used as a reference, on the other Verilog simulation call.
matlab-and-verilog-fir4_3
- 四抽头FIR滤波器matlab,verilog顶层，子模块，以及testbench代码-Four tap FIR filter matlab, verilog top, sub modules, as well as the testbench code
testbench_learn
- 自己写的一个移位寄存器的实例，该例子主要用来讲述verilog中的testbench的写作，以及在testbench中怎样使用task，以使仿真更加的高效简洁-Write your own instance of a shift register, which is mainly used to describe examples of verilog testbench writing, as well as how to use the testbench in the task, to m
8051core-Verilog
- 基于Verilog的 8051 IP核 内含 Testbench-The 8051 IP core based on Verilog
shift-register-and-testbench
- Shift register and testbench in verilog
xuliejianceqi
- 序列检测器00101，包括源代码，testbench，ise13.4测试以及综合通过等说明文档。-Sequence detector 00101, the state machine verilog, testbench, ise13.4 simulation map. The test is successful
ADF4113_loader
- ADF4113 loader written on Verilog + Icarus Verilog testbench
serial-cordic-verilog
- implementation of cordic algorithm for many aplication like cos, sinus, polar to rectangular conversion and rectangular to polar conversion. It s written in verilog language and testbench is included
Verilog-code-for-finding-GCD
- State machine implemented in verilog to find GCD of two 8 bit numbers. Two files are included (module and its testbench)
sv_lab_switch
- system verilog ASIC 验证平台编写详细实例-system verilog testbench for ASIC
Uart-Verilog
- verilog实现串口通讯，包括verilog代码和testbench代码-verilog serial communication, including the verilog code and testbench Code
gen_tb
- 自己写的perl程序，可以根据逻辑代码的top文件自动生成verilog的testbench，方便做simulation，提高效率-perl program,written by myself, can automatically generate verilog testbench according to the logic of the code top file, easy to do simulation, improve efficiency
64Bit-Look-Ahead-Adder-Verilog-Code-with-Testbenc
- 64Bit Look Ahead Adder Verilog Code with Testbench
DES-Verilog-master
- DES加密算法硬件verilog实现，包含testbench，加密主模块encrypt，明文变换模块LRToCiphertextConverter，NextRi模块等子模块。-DES encrypt verilog
testbench.sv
- RS 编码和解码Verilog Code, 实现了RS（544,514)的编码和译码；--RS Coding and Decoding Verilog code， implement RS（544,514)