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dma(including-driver).xapp1052
- xilinx 官方dma 的verilog实现，包含windows和linux驱动。-XILINX s dma design of verilog ,including windows driver and linux driver .
Manchester-Encoding-Verilog
- THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR
MP3-design-using-verilog
- 基于Xilinx XUPV2P平台(FPGA开发板)的MP3播放器设计-MP3 player design based on the the Xilinx XUPV2P platform (FPGA development board)
myvga
- 串口程序 verilog xilinx -Serial program Verilog xilinx
counter
- 计算数程序 verilog xilinx-Calculate the number of procedures Verilog xilinx
iic
- iic 通信 verilog xilinx -the iic communication Verilog xilinx
Xilinx-verilog
- xilinx培训源码及工程文件,给予spartan 3E开发板的！希望对初学者有所帮助-Xilinx training codes and project！！ IT‘s worth to learn！！
xapp495
- 居然没有找到verilog 这是xilinx的一个hdmi的标准核 我测试使用通过-Actually did not find verilog xilinx an hdmi standard nuclear my test use by
verilog
- it is xilinx SDR SDRAM controller core
verilog-hdl
- 很少有完整介绍ISE环境下FPGA开发的资料，这是在Xilinx ISE开发平台下进行FPGA设计比较好的教程，感觉挺不错的-there is few full descr iption ISE FPGA development environment information, which is in the Xilinx ISE development platform for FPGA design is a good tutorial, I feel pretty good
ddr2
- xilinx ddr2 mig核读写控制 verilog -xilinx mig write and read timing
Rashed
- simple Adder in verilog (xilinx)
XILINX DDR2
- xilinx ddr2 ip核的verilog例子
verilog coding
- verilog coding EE 517, homework2, using xilinx
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
Timer
- 基于verilog xilinx spartan 3e100的秒表计时器-Based verilog xilinx spartan 3e100 stopwatch timer
segment
- 基于verilog xilinx spartan 的7段管显示-7-segment tube display based on verilog xilinx spartan
DDR3design-on-xilinx
- 在xilinx平台上实现的ddr3的设计，verilog-ddr3,design on xilinx,verilog
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
UART-Verilog-source
- Verilog编写UART串口例程，实现FPGA与上位机串口通信，利用ASCII码进行大小写转换，在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test