搜索资源列表
VGA
- 基于Xilinx SPARTAN-3E开发板 的VGA实验代码，VHDL编写，非常适合初学者学习FPGA实现VGA控制-Based on Xilinx SPARTAN-3E development board VGA test code, VHDL written, very suitable for beginners to learn to achieve VGA control FPGA
vhdl
- 自动打铃系统的VHDL设计中的状态机，自己已经检验过了完全正确-STATEMACHING OF AUTO RING WITH VHDL.
SPWM
- VHDL采用自然采样法写的SPWM，里面有正弦表，可以通过外接输入正弦波和三角波的频率。 -VHDL using written natural sampling SPWM, there are sine table, you can enter through the external sinusoidal and triangular wave frequency.
16bitalu
- 16 bit alu using the vhdl it has 16 function perform by control unit with 4 control signal
bc6502
- VHDL实现的一个完整版的6502CPU硬件描述代码，包含了6502CPu的所有功能，附带VGA驱动以及输入输出控制-VHDL implementation of a full version of 6502CPU hardware descr iption code, and includes all the features of 6502CPu, incidental VGA driver, as well as input and output control
oc_mkjpeg
- Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design.
IIRfilterFPGA
- 介绍了IIR 滤波器的FPGA 实现方法,给出了 IIR 数字滤波器的时序控制、延时、补码乘法和累加四个模块的设计方法,并用VHDL和FPGA 器件实现了IIR 数字滤波。-Introduction of the IIR filter FPGA implementation method of IIR digital filter timing control, delay, multiplication and accumulation complement the four modules
sdram_design
- SDRAM存取控制器设计书，包含标准的SDRAM读写控制功能，和自动刷新功能。对VHDL设计初学者很有帮助。密码MMCTEAM。-SDRAM access controller design books, contain standard SDRAM read and write control functions, and auto refresh function. VHDL design helpful for beginners. Password MMCTEAM.
FPGA_VHDL_code
- FPGA学习非常珍贵的资料，包括USB、UART、I2C、Ethernet、VGA、CAN等总线的VHDL实现，可以直接应用于实际项目中。需要的请下载。 -FPGA to learn very valuable information, including USB, UART, I2C, Ethernet, VGA, CAN bus, such as VHDL to achieve, can be directly applied to actual projects. Need to do
turbo
- turbo的VHDL代码 比较好啊 易后大家多多交流啊-Comparison of the VHDL code for turbo Well you lot of the easy exchange of ah
UART
- 这是VHDL编写的UART源码，测试成功，欢饮下载-It is written in UART VHDL source code, the test is successful, Huanyin download
datapath_fifo
- datapath_fifo used in DMA contect PCI in the DAB system the format of this file is VHDL
LMX2531_PLL_module
- 利用FPGA完成对锁相芯片LMX2531初始化，语言为VHDL.-this module solute the PLL chip LMX2531 event ,using FPGA with VHDL.
VHDL_code
- 基于FPGA的AD,DA,LCD,LED,CAN,I2C,PS2,VGA以及一些通讯ASK,FSK等的VHDL源程序，所有程序已通过调试，需要的拿走。-FPGA-based AD, DA, LCD, LED, CAN, I2C, PS2, VGA, and some communications ASK, FSK, etc. VHDL source code, all procedures have been debugging, need to take.
88fifovhdl
- 88位进出缓冲器8*8位的fifo数据缓冲器的vhdl源程序 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-88 out of 8* 8-bit buffer fifo data buffer vhdl source Bianle Ge 8* 8-bit data buffer fifo vhdl source code is compiled through quartusII4.2 successful progra
12864VHDL
- 采用VHDL语言编写的程序让FPGA驱动12864显示作图和划线。-Using a program written in VHDL to FPGA mapping and marking display driver 12864.
VHDLDATACLOCK
- 本课程设计完成了数字电子钟的设计，数字电子钟是一种用数字显示秒、分、时的计时装置，由于数字集成电路技术的发展和采用了先进的石英技术，它使数字钟具有走时准确、性能稳定、携带方便等优点。数字钟已成为人们日常生活中必不可少的必需品，广泛用于个人家庭以及办公室等公共场所，给人们的生活带来极大的方便。在这里我们将已学过的比较零散的数字电路的知识有机的、系统的联系起来用于实际，来培养我们的综合分析和设计电路的能力。-VHDL dataclock
four_adder
- 应用一位全加器的VHDL语言，创建一位全加器符号，用原理图完成四位全加器-Application of a full adder VHDL language, to create a full-adder symbol, with the principle of the completion of four full adder diagram
ram
- 一个用VHDL语言编写的双端口存储器程序，可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using
ps2
- vhdl实现ps2接口的程序,可以接受键盘的输入或者鼠标的输入.-VHDL procedures to achieve ps2 interface can accept keyboard input or mouse input.