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jdcbzh.使用VHDL语言实现串并转换模块的实现
- 使用VHDL语言实现串并转换模块的实现，可在QUARTUS上实现,Use VHDL language string and conversion module, but in QUARTUS
keydebounce.rar
- FPGA中按键弹跳消除模块的研究与应用，原理和例子都非常好,FPGA to eliminate bounce in key research and application modules, principles and examples are very good
parell_to_serial.rar
- 该模块主要完成并串转换功能。其中system_clk是输入并行时钟的频率，它是串行时钟serial_clk的八倍。byte_data_en是输入并行数据使能信号，byte_data是输入并行数据。serial_data是转换后的串行数据，bit_data_enable是串行数据有效信号。,The module main is completed and the string conversion functions. System_clk which is an input parallel c
uart.rar
- VHDL语言编写的全功能串口模块（包含DTR，RTS等管脚），在CPLD器件上测试通过,VHDL language, full-featured serial modules (including DTR, RTS pin, etc.), in the CPLD device test
uart.rar
- 实现串并口通信,共有发送和接受两个模块。,Strings parallel to achieve communication, send and receive a total of two modules.
sd_reader.rar
- SD卡读卡器模块的VHDL及软件驱动代码，可作为外设挂接在Avalon总线上。支持以SD模式、4线模式读取。在24MHz时钟驱动下读取速率可达8MByte/s,SD card reader module and software drivers VHDL code, can be articulated as a peripheral bus in Avalon. To support the SD model, 4-wire mode read. Driven by the 24MHz clo
SDH.rar
- 他是一个SDH上行代码，有八个模块组成的，能够传输以太网的数据 ,He is an SDH uplink code, there is composed of eight modules, Ethernet can transmit data
CIC_deci4.rar
- cic抽取滤波器ip核，用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证,CIC decimation by 4 filter，used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
I2C.rar
- FPGA实现模拟I2C协议的过程，包括三个模块，i2c_master_bit_ctrl.v完成位传输功能、i2c_master_byte_ctrl.v完成字节传输功能，i2c_master_top.v完成整个程序的控制功能，并提供给外部程序的接口。 ,I2C Analog FPGA implementation of the Protocol process, including the three modules, i2c_master_bit_ctrl.v achieve bit tran
shuzi.rar
- 数字电子钟设计，整点报时，时分秒分模块设计，另附实验报告和实验结果，内容详细不容错过,The design of digital electronic clock, the whole point of time when minutes and seconds sub-module design, an additional test reports and laboratory test results, the details not to be missed
FPGA_nCLK.rar
- VHDL语言的高频时钟分频模块。一种新的分频器实现方法。,VHDL language at the high-frequency clock frequency modules. Divider to achieve a new method.
shibo(ok).rar
- 基于cycloneII和MSP430单片机的示波器，利用spi模块进行双机通信,Based on the MSP430 MCU and cycloneII oscilloscope, using dual-spi communication module
EP2C20_TEST.rar
- 内含无刷电机驱动VHDL模块，读码盘4倍频模块，并用NIOS核实现简单无刷电机闭环控制。,Brushless motor driver includes VHDL modules, reading frequency module plate 4, and nuclear NIOS simple closed-loop control of brushless motor.
-VHDL
- 本报告分两部分： 1 由matlab计算FIR数字滤波器的滤波系数； 2 用VHDL语言设计逻辑电路，再通过QUARTUS II 软件，将各个模块的电路封装成期间，在顶层设计中通过连线，完成整个系统。 -FIR digital filters based on VHDL
EEPROM_RD_WR.rar
- 本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。,This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (e
ltc1196.rar
- TLC1196串行AD控制模块，可以实现对电压的信号采集，并以串行的方式传送到FPGA中,TLC1196 Serial AD control module can be achieved on the voltage of the signal acquisition, and serial transmission of the FPGA
EDA.rar
- 这里边有EDA设计常用模块的源代码，FFT,DDS PS2_keyboard，VGA等，有学FPGA的就参考一下吧,Here the design of commonly used modules have EDA source code, FFT, DDS PS2_keyboard, VGA and so on, have places on the FPGA reference yourself
butterfly.rar
- 蝶形运算，可用于DCT变换，FFT变换的模块,Butterfly computation, can be used for DCT transform, FFT transform module
VHDL_procedures.rar
- VHDL程序来让蜂鸣器发出音乐的声音 这种电路设计要分好几个模块 主要思路是用ROM记录乐谱 然后用分频器分频 还有就是用计数器读取乐谱 另外还可以扩展 使其显示音符 这是一个做好了的 就是ROM没填谱,VHDL procedures are in place to allow the voice of music The buzzer sounded a circuit design that several sub-modules to the ma
baseband_verilog.rar
- verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m