搜索资源列表
ADDER
- VHDL语言的带控制端口的加法器，实现加法运算。-VHDL language, with a control port of the adder to achieve addition operation.
DesignofFloatingPointCalculatorBasedonFPGA
- 给出系统的整体框架设计和各模块的实现，包括芯片的选择、各模块之间的时序以及控制、每个运算模块详细的工作原理和算法设计流程；通过VHDL语言编程来实现浮点数的加减、乘除和开方等基本运算功能；在Xilinx ISE环境下，对系统的主要模块进行开发设计及功能仿真，验证 了基于FPGA的浮点运算。 -The overall framework of system design and realization of each module which contain selection of ch
butterfly
- 蝶形运算的VHDL代码 已通过quartusii编译仿真-VHDL Butterfly computing simulation code has been compiled by quartusii
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
190.7_Freq_divider
- QUARTUS II环境下VHDL编写的小数点分频器程序，实现190.7分频，可以将50MHz时钟频率分频成约等于2^21Hz频率，方便特殊情况下的运算-QUARTUS II, prepared under the decimal divider VHDL program to achieve 190.7 frequency, you can divide into a 50MHz clock frequency is about equal to 2 ^ 21Hz frequency, eas
add8
- 用VHDL语言实现的八位计数器 可进行简单的加减乘除运算-It is a counting device with eight-bit that could plus ,subtract ,multiply and divide.
alu
- VHDL描述的alu，可以进行基本的运算，在quartus2环境下运行。实验课作业。-VHDL descr iption of the alu, the basic operations can be carried out in quartus2 environments. Experimental course work.
multiply
- 实验报告中完成以下功能：在maxplus2 环境下，完成4bit × 4bit 运算功能，并模拟显示出相关内容，设计动态扫描显示电路，显示两位字符，以便用在4bit × 4bit运算中。 （附源程序代码）-multiplay under maxplus2，use VHDL
dsp_test
- 利用FPGA实现DSP浮点运算，VHDL代码-FPGA implementation using floating-point DSP, VHDL code
summator
- 加法器是产生数的和的装置。常用作计算机算术逻辑部件，执行逻辑操作、移位与指令调用。在电子学中，加法器是一种数位电路，其可进行数字的加法计算。在现代的电脑中，加法器存在于算术逻辑单元之中。 加法器可以用来表示各种数值，如：BCD、加三码，主要的加法器是以二进制作运算。加法器可以用组合逻辑电路实现也可以用VHDL语言实现。-Adder is generated and the number of devices. Arithmetic logic unit is used as a computer
cc14585
- 用vhdl语言编译一个8位二进制求补器 对输入的数字进行求补运算-Vhdl language compiler with an 8-bit binary complement of the input device to complement the number of operations
vhdl_16CPU
- 16位CPU设计，采用VHDL语言，自带测试汇编语言，能实现基本运算和移位、跳转等操作-16-bit CPU design, using VHDL language, self-test assembly language, to achieve the basic operations and shift operations such as jump
95637012Multiplier
- 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。- This file contains all the entity-architectures for a complete-- k-bit x k-bit Booth multiplier.-- the design makes use of
VHDLshixianCPU2
- vhdl实现cpu用verilog写的8位CPU源码，通过汇编语言可以实现加减乘左移右移等运算。并通过ASC流程可以模拟出其内部电路结构。代码，截图，readme在文件夹中-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process throu
ccmul
- FFT中 旋转因子8位复数乘法的VHDL程序，3次实数乘法和3次加减法运算，-FFT twiddle factor of the VHDL program, 3 times real multiplication and subtraction 3
test5
- 用VHDL设计8位算术逻辑运算器，并将运算结果显示通过俩个七段数码管显示-Design with VHDL 8-bit arithmetic and logic devices, and computing results show that by two seven-segment LED display
h_adder
- 半加器的实现，利用VHDL语言实现半加器的运算-Half adder implementation using VHDL language and a half-adder operation
ls139
- 全加器程序编写，用VHDL语言实现四位全加器的加法运算-Full adder programming, using VHDL language to achieve the addition of four full-adder operation
chufaqi
- 介绍了一种使用可编程逻辑器件FPGA和VHDL语言实现32位除法器的设计方法。该除法器不仅可以实现有符号数运算,也可以实现无符号数的运算。-A programmable logic device FPGA and VHDL design of the 32 divider. The divider can be achieved not only symbolic arithmetic, unsigned op.
RISC_CPU
- VHDL语言设计的RISC_CPU，分为八个基本部件分模块构建，分别为时钟发生器，指令寄存器，累加器，算术逻辑运算单元，数据控制器，状态控制器，程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator,